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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and changes will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion flash memory data sheet tm
ds05-20909-1e fujitsu semiconductor data sheet page mode flash memory cmos 128m (8m 16) bit mbm29qm12dh -60 n description the mbm29qm12dh is 128 m-bit, 3.0 v-only page mode and dual operation flash memory organized as 8m words of 16 bits each. the device is offered in 56-pin tsop and 80-ball fbga package. this device is designed to be programmed in-system with the standard system 3.0 v vcc supply. 12.0 v vpp and 5.0 v vcc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. (continued) n product line up n packages part no. mbm29qm12dh60 v cc = 3.0 v v ccq = 2.7 v to 3.6 v v ccq = 1.65 v to 1.95 v max random address access time (ns) 60 70 max page address access time (ns) 20 30 max ce access time (ns) 60 70 max oe access time (ns) 20 30 56-pin plastic tsop (1) (fpt-56p-m01) 80-pin plastic fbga (bga-80p-m04) + 0.6 v C0.3 v
mbm29qm12dh -60 2 (continued) the device provides truly high performance non-volatile flash memory solution. the device offers fast page access times of 20 ns with random access times of 60 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the page size is 8 words. the dual operation function provides simultaneous operation by dividing the memory space into four banks. the device can improve overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank with zero latency. this releases the system from waiting for the completion of program or erase operations. the device is command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state- machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the device is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. typically, each 32k words sector can be programmed and verified in about 0.3 seconds. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margins. any individual sector is typically erased and verified in 0.5 second. (if already preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the device is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , output pin. once the end of a program or erase cycle has been completed, the device internally resets to the read mode. fujitsus flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. the device memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the words are programmed one word at a time using the eprom programming mechanism of hot electron injection.
mbm29qm12dh -60 3 n features ?0.13 m m m m m process technology ? single 3.0 v read, program and erase minimized system level power requirements ? simultaneous read/write operations (dual bank) ? flexbank tm * 1 bank a: 16 mbit (4 kw 8 and 32 kw 31) bank b: 48 mbit (32 kw 96) bank c: 48 mbit (32 kw 96) bank d: 16 mbit (4 kw 8 and 32 kw 31) ? enhanced v i/o (v ccq ) feature input / output voltage generated on the device is determined based on the v i/o level v i/o (v ccq ) range : 2.7 v to 3.6 v or 1.65 v to 1.95 v ? high performance page mode 20 ns maximum page access time (60 ns random access time) (3 v v i/o ) ?8 words page ( 16) ? compatible with jedec-standard commands uses same software commands as e 2 proms ? minimum 100,000 program/erase cycles ? sector erase architecture eight 4k words, two hundred fifty-four 32k words, eight 8k words sectors. any combination of sectors can be concurrently erased. also supports full chip erase ? dual boot block 164k words boot block sectors, 8 at the top of the address range and 8 at the bottom of the address range ? hiddenrom region 64 words for factory and 64 words for customer of hiddenrom, accessible through a new hiddenrom enable command sequence factory serialized and protected to provide a secure electronic serial number (esn) ?wp /acc input pin at v il , allows protection of outermost 2 4k words on both ends of boot sectors, regardless of sector protection/unprotection status at v ih , allows removal of boot sector protection at v acc , increases program performance ? embedded erase tm * 2 algorithms automatically preprograms and erases the chip or any sector ? embedded program tm * 2 algorithms automatically writes and verifies data at specified address ?data polling and toggle bit feature for detection of program or erase cycle completion ? ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion ? automatic sleep mode when addresses remain stable, the device automatically switches itself to low power mode. ?low v cc write inhibit 2.5 v (continued)
mbm29qm12dh -60 4 (continued) ? program suspend/resume suspends the program operation to allow a read in another byte ? erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device ? in accordance with cfi (c ommon f lash memory i nterface) ? hardware reset pin (reset ) hardware method to reset the device for reading array data ? new sector protection persistent sector protection password sector protection *1 : flexbank tm is a trademark of fujitsu limited, japan. *2 : embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc.
mbm29qm12dh -60 5 n pin assignment (continued) reset ry/by a 0 a 1 a 2 a 3 a 4 a 5 v cc dq 0 dq 1 dq 2 dq 3 v ssq v ccq dq 4 dq 5 dq 6 dq 7 v ss n.c. a 6 a 7 a 8 a 9 a 10 a 11 a 12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 tsop (1) (top view) wp/acc we n.c. a 22 a 21 a 20 oe n.c. ce v ss dq 15 dq 14 dq 13 dq 12 v ssq v ccq dq 11 dq 10 dq 9 dq 8 v cc a 19 a 18 a 17 a 16 a 15 a 14 a 13 (marking side) (fpt-56p-m01)
mbm29qm12dh -60 6 (continued) n pin descriptions mbm29qm12dh pin configuration table pin function a 22 to a 0 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable reset hardware reset wp /acc hardware write protection/ program acceleration ry/by ready/busy output n.c. pin not connected internally v ss device ground v cc device power supply v ssq input & output buffer ground v ccq input & output buffer power supply a8 b8 l8 m8 n.c. n.c. n.c. n.c. c7 d7 e7 f7 g7 h7 j7 k7 a 13 a 12 a 14 a 15 a 16 dq 15 v ss c6 d6 e6 f6 g6 h6 j6 k6 a 9 a 8 a 10 a 11 dq 7 dq 14 dq 13 dq 6 c5 d5 e5 f5 g5 h5 j5 k5 we reset a 21 a 19 dq 5 dq 12 v cc dq 4 c4 d4 e4 f4 g4 h4 j4 k4 ry/by wp/acc a 18 a 20 dq 2 dq 10 dq 11 dq 3 c3 d3 e3 f3 g3 h3 j3 k3 a 7 a 17 a 6 a 5 dq 0 dq 8 dq 9 dq 1 c2 d2 e2 f2 g2 h2 j2 k2 a 3 a 4 a 2 a 1 a 0 ce oe v ss a1 b1 l1 m1 n.c. n.c. n.c. n.c. (marking side) d8 e8 f8 g8 h8 j8 d1 e1 f1 g1 h1 j1 v ssq v ccq n.c. n.c. n.c. n.c. v cc v ccq v ssq n.c. a 22 n.c. n.c. a2 b2 n.c. n.c. a7 b7 n.c. n.c. l2 m2 n.c. n.c. l7 m7 n.c. n.c. c1 n.c. k1 n.c. k8 n.c. c8 n.c. fbga (top view) (bga-80p-m04)
mbm29qm12dh -60 7 n block diagram n logic symbol v cc v ss a 22 to a 0 reset we ce oe wp/acc dq 15 to dq 0 dq 15 to dq 0 bank a address bank c address bank b address bank d address state control & command register status ry/by control cell matrix 16 mbit (bank a) x-decoder y-gating cell matrix 16 mbit (bank d) x-decoder y-gating cell matrix 48 mbit (bank b) x-decoder y-gating cell matrix 48 mbit (bank c) x-decoder y-gating 23 a 22 to a 0 oe ce reset dq 15 to dq 0 16 wp/acc we ry/by
mbm29qm12dh -60 8 n device bus operation mbm29qm12dh user bus operations table legend: l = v il , h = v ih , x = v il or v ih , = pulse input. see dc characteristics for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see mbm29qm12dh command definitions table in n device bus operation. *2 : we can be v il if oe is v il , oe at v ih initiates the write operations. *3 : refer to section on sector protection. *4 : v ccq = 2.7 v to 3.6 v for 60 ns v ccq = 1.65 v to 1.95 v for 70 ns. *5 : also used for the extended sector group protection. *6 : protect outermost 2 4k words on both ends of the boot block sectors (sa0, sa1, sa268, sa269) . operation ce oe we a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 9 dq 15 to dq 0 reset wp / acc auto-select manufacturer code* 1 llhllllxxllv id code h x auto-select device code* 1 llhhlllxxllv id code h x extended auto-select device code* 2 llhlhhhxxllv id code h x l lhhhhhxx l lv id code h x read* 3 llha 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 9 d out hx standby h xxxxxxxxxxxhigh-z h x output disable lhhxxxxxxxxxhigh-z h x write (program/erase) l h l a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 9 d in hx enable sector group protection* 3, * 4 lv id lhllllllv id xhx verify sector group protection* 3, * 4 llhlhllllllv id code h h boot block sector write protection* 6 xxxxxxxxxxxx x h l temporary sector group unprotection* 5 xxxxxxxxxxxx x v id x reset xxxxxxxxxxxxhigh-z l x
mbm29qm12dh -60 9 mbm29qm12dh command definitions table (continued) command sequence bus write cy- cles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data read/reset 1 xxxh f0h ra rd read/reset 3 555h aah 2aah 55h 555h f0h ra rd autoselect 3 555h aah 2aah 55h (ba) 555h 90h program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h program/erase suspend 1bab0h program/erase resume 1 ba 30h set to fast mode 3 555h aah 2aah 55h 555h 20h fast program 2 xxxh a0h pa pd reset from fast mode * 1 2 ba 90h xxxh * 4 f0h extended sector group protection * 2 4 xxxh 60h sga + wph 60h sga + wph 40h sga + wph sd query 1 (ba) 55h 98h hiddenrom entry 3 555h aah 2aah 55h 555h 88h hiddenrom program * 3 4 555h aah 2aah 55h 555h a0h (hra) pa pd hiddenrom exit * 3 4 555h aah 2aah 55h (hrba) 555h 90h xxxh 00h hiddenrom protect * 3 6 555h aah 2aah 55h 555h 60h opbp 68h opbp 48h xxxh rd (0) password program 4 555h aah 2aah 55h 555h 38h xx0h pd0 555h aah 2aah 55h 555h 38h xx1h pd1 555h aah 2aah 55h 555h 38h xx2h pd2 555h aah 2aah 55h 555h 38h xx3h pd3 password unlock 7 555h aah 2aah 55h 555h 28h xx0h pd0 xx1h pd1 xx2h pd2 xx3h pd3 password verify 4 555h aah 2aah 55h 555h c8h pwa pwd
mbm29qm12dh -60 10 (continued) legend: ra = address of the memory location to be read pa = address of the memory location to be programmed addresses are latched on the falling edge of the write pulse. sa = address of the sector to be erased. the combination of a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 will uniquely select any sector. ba = bank address. address setted by a 22 , a 21 , a 20 will select bank a, bank b, bank c and bank d. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of write pulse. sga = sector group address to be protected. wph = (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (0, 0, 0, 0, 0, 0, 1, 0) sd = sector group protection verify data. output 01h at protected sector group addresses and output 00h at unprotected sector group addresses. hra = address of the hiddenrom area word mode : 000000h to 00007fh hrba = bank address of the hiddenrom area (a 22 = a 21 = a 20 = v il ) rd (0) = read data bit. if programmed, dq 0 = 1, if erase, dq 0 = 0 rd (1) = read data bit. if programmed, dq 1 = 1, if erase, dq 1 = 0 opbp = (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (0, 0, 0, 1, 1, 0, 1, 0) pwa/pwd = password address/password data pl = (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (0, 0, 0, 0, 1, 0, 1, 0) spml = (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (0, 0, 0, 1, 0, 0, 1, 0) wp = (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) is (0, 0, 0, 0, 0, 0, 1, 0) command sequence bus write cy- cles req d first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle seventh bus write cycle addr. data addr. data addr. data addr. data addr. data addr. data addr. data password mode locking bit program 6 555h aah 2aah 55h 555h 60h pl 68h pl 48h xxxh rd (0) persistent protection mode locking bit program 6 555h aah 2aah 55h 555h 60h spml 68h spml 48h xxxh rd (0) ppb program 6 555h aah 2aah 55h 555h 60h sga + wp 68h sga + wp 48h xxxh rd (0) ppb verify 4 555h aah 2aah 55h (ba) 555h 90h sga + wp rd (0) all ppb erase 4 555h aah 2aah 55h 555h 60h wp 60h sga + wp 40h xxxh rd (0) ppb lock bit set 3 555h aah 2aah 55h 555h 78h ppb lock bit verify 4 555h aah 2aah 55h (ba) 555h 58h sa rd (1) dpb write 4 555h aah 2aah 55h 555h 48h sa x1h dpb erase 4 555h aah 2aah 55h 555h 48h sa x0h dpb verify 4 555h aah 2aah 55h (ba) 555h 58h sa rd (0)
mbm29qm12dh -60 11 *1 : this command is valid during fast mode. *2 : this command is valid while reset = v id . *3 : this command is valid during hiddenrom mode. *4 : the data 00h is also acceptable. *5 : command combinations not described in mbm29qm12dh command definitions table in n device bus operation are illegal. notes : address bits a 22 to a 11 = x = h or l for all address commands except for pa, sa, ba, sga, opbp, pwa, pl, spml, wp, wph. bus operations are defined in mbm29qm12dh user bus operations table and mbm29qm12dh command definitions table in n device bus operation. the system should generate the following address patterns: word mode : 555h or 2aah to addresses a 10 to a 0 both read/reset commands are functionally equivalent, resetting the device to the read mode. mbm29qm12dh sector group protection verify autoselect codes table *1 : sector group can be protected by "sector group protection", "extended sector group protection", and "new sector protection(ppb protection). outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses. *2 : when v id is applied to a 9 , both bank 1 and bank 2 are put into autoselect mode, which makes simultaneous operation unable to be executed. consequently, specifying the bank address is not required. however, the bank address needs to be indicated when autoselect mode is read out at command mode, because then it becomes possible to activate simultaneous operation. *3 : a read cycle at address (ba) 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes, will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh. extended autoselect code table type a 22 to a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 code (hex) manufactures code ba* 2 v il v il xxv il v il v il v il 04h device code ba* 2 v il v il xxv il v il v il v ih 227eh extended device code* 3 ba* 2 v il v il xxv ih v ih v ih v il 2220h v il v il xxv ih v ih v ih v ih 2200h sector group protection sector group addresses v il v il v il v il v il v il v ih v il 01h* 1 extended device code (indicator bits) ba* 2 v il v il v il v il v il v il v ih v ih dq 7 - factory lock bit 1 = locked, 0 = not locked dq 6 - customer lock bit 1 = locked, 0 = not locked type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacturers code04h000000 0000000100 device code 227eh 0 0 1000 1001111110 extended device code 2220h 0 0 1000 1000100000 2200h 0 0 1000 1000000000 ppb protection 01h000000 0000000001 ppb unprotection 00h000000 0000000000
mbm29qm12dh -60 12 n flexible sector-erase architecture sector address table ( bank a ) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank a sa0 0 0 0 0 0 0 0 0 0 0 0 4 000000h to 000fffh sa1 0 0 0 0 0 0 0 0 0 0 1 4 001000h to 001fffh sa2 0 0 0 0 0 0 0 0 0 1 0 4 002000h to 002fffh sa3 0 0 0 0 0 0 0 0 0 1 1 4 003000h to 003fffh sa4 0 0 0 0 0 0 0 0 1 0 0 4 004000h to 004fffh sa5 0 0 0 0 0 0 0 0 1 0 1 4 005000h to 005fffh sa6 0 0 0 0 0 0 0 0 1 1 0 4 006000h to 006fffh sa7 0 0 0 0 0 0 0 0 1 1 1 4 007000h to 007fffh sa8 0 0 0 0 0 0 0 1 x x x 32 008000h to 00ffffh sa9 0 0 0 0 0 0 1 0 x x x 32 010000h to 017fffh sa10 0 0 0 0 0 0 1 1 x x x 32 018000h to 01ffffh sa11 0 0 0 0 0 1 0 0 x x x 32 020000h to 027fffh sa12 0 0 0 0 0 1 0 1 x x x 32 028000h to 02ffffh sa13 0 0 0 0 0 1 1 0 x x x 32 030000h to 037fffh sa14 0 0 0 0 0 1 1 1 x x x 32 038000h to 03ffffh sa15 0 0 0 0 1 0 0 0 x x x 32 040000h to 047fffh sa16 0 0 0 0 1 0 0 1 x x x 32 048000h to 04ffffh sa17 0 0 0 0 1 0 1 0 x x x 32 050000h to 057fffh sa18 0 0 0 0 1 0 1 1 x x x 32 058000h to 05ffffh sa19 0 0 0 0 1 1 0 0 x x x 32 060000h to 067fffh sa20 0 0 0 0 1 1 0 1 x x x 32 068000h to 06ffffh sa21 0 0 0 0 1 1 1 0 x x x 32 070000h to 077fffh sa22 0 0 0 0 1 1 1 1 x x x 32 078000h to 07ffffh sa23 0 0 0 1 0 0 0 0 x x x 32 080000h to 087fffh sa24 0 0 0 1 0 0 0 1 x x x 32 088000h to 08ffffh sa25 0 0 0 1 0 0 1 0 x x x 32 090000h to 097fffh sa26 0 0 0 1 0 0 1 1 x x x 32 098000h to 09ffffh sa27 0 0 0 1 0 1 0 0 x x x 32 0a0000h to 0a7fffh sa28 0 0 0 1 0 1 0 1 x x x 32 0a8000h to 0affffh sa29 0 0 0 1 0 1 1 0 x x x 32 0b0000h to 0b7fffh sa30 0 0 0 1 0 1 1 1 x x x 32 0b8000h to 0bffffh sa31 0 0 0 1 1 0 0 0 x x x 32 0c0000h to 0c7fffh sa32 0 0 0 1 1 0 0 1 x x x 32 0c8000h to 0cffffh sa33 0 0 0 1 1 0 1 0 x x x 32 0d0000h to 0d7fffh sa34 0 0 0 1 1 0 1 1 x x x 32 0d8000h to 0dffffh sa35 0 0 0 1 1 1 0 0 x x x 32 0e0000h to 0e7fffh sa36 0 0 0 1 1 1 0 1 x x x 32 0e8000h to 0effffh sa37 0 0 0 1 1 1 1 0 x x x 32 0f0000h to 0f7fffh sa38 0 0 0 1 1 1 1 1 x x x 32 0f8000h to 0fffffh
mbm29qm12dh -60 13 sector address table ( bank b ) (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa39 0 0 1 0 0 0 0 0 x x x 32 100000h to 107fffh sa40 0 0 1 0 0 0 0 1 x x x 32 108000h to 10ffffh sa41 0 0 1 0 0 0 1 0 x x x 32 110000h to 117fffh sa42 0 0 1 0 0 0 1 1 x x x 32 118000h to 11ffffh sa43 0 0 1 0 0 1 0 0 x x x 32 120000h to 127fffh sa44 0 0 1 0 0 1 0 1 x x x 32 128000h to 12ffffh sa45 0 0 1 0 0 1 1 0 x x x 32 130000h to 137fffh sa46 0 0 1 0 0 1 1 1 x x x 32 138000h to 13ffffh sa47 0 0 1 0 1 0 0 0 x x x 32 140000h to 147fffh sa48 0 0 1 0 1 0 0 1 x x x 32 148000h to 14ffffh sa49 0 0 1 0 1 0 1 0 x x x 32 150000h to 157fffh sa50 0 0 1 0 1 0 1 1 x x x 32 158000h to 15ffffh sa51 0 0 1 0 1 1 0 0 x x x 32 160000h to 167fffh sa52 0 0 1 0 1 1 0 1 x x x 32 168000h to 16ffffh sa53 0 0 1 0 1 1 1 0 x x x 32 170000h to 177fffh sa54 0 0 1 0 1 1 1 1 x x x 32 178000h to 17ffffh sa55 0 0 1 1 0 0 0 0 x x x 32 180000h to 187fffh sa56 0 0 1 1 0 0 0 1 x x x 32 188000h to 18ffffh sa57 0 0 1 1 0 0 1 0 x x x 32 190000h to 197fffh sa58 0 0 1 1 0 0 1 1 x x x 32 198000h to 19ffffh sa59 0 0 1 1 0 1 0 0 x x x 32 1a0000h to 1a7fffh sa60 0 0 1 1 0 1 0 1 x x x 32 1a8000h to 1affffh sa61 0 0 1 1 0 1 1 0 x x x 32 1b0000h to 1b7fffh sa62 0 0 1 1 0 1 1 1 x x x 32 1b8000h to 1bffffh sa63 0 0 1 1 1 0 0 0 x x x 32 1c0000h to 1c7fffh sa64 0 0 1 1 1 0 0 1 x x x 32 1c8000h to 1cffffh sa65 0 0 1 1 1 0 1 0 x x x 32 1d0000h to 1d7fffh sa66 0 0 1 1 1 0 1 1 x x x 32 1d8000h to 1dffffh sa67 0 0 1 1 1 1 0 0 x x x 32 1e0000h to 1e7fffh sa68 0 0 1 1 1 1 0 1 x x x 32 1e8000h to 1effffh sa69 0 0 1 1 1 1 1 0 x x x 32 1f0000h to 1f7fffh sa70 0 0 1 1 1 1 1 1 x x x 32 1f8000h to 1fffffh sa71 0 1 0 0 0 0 0 0 x x x 32 200000h to 207fffh sa72 0 1 0 0 0 0 0 1 x x x 32 208000h to 20ffffh sa73 0 1 0 0 0 0 1 0 x x x 32 210000h to 217fffh sa74 0 1 0 0 0 0 1 1 x x x 32 218000h to 21ffffh sa75 0 1 0 0 0 1 0 0 x x x 32 220000h to 227fffh sa76 0 1 0 0 0 1 0 1 x x x 32 228000h to 22ffffh sa77 0 1 0 0 0 1 1 0 x x x 32 230000h to 237fffh
mbm29qm12dh -60 14 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa78 0 1 0 0 0 1 1 1 x x x 32 238000h to 23ffffh sa79 0 1 0 0 1 0 0 0 x x x 32 240000h to 247fffh sa80 0 1 0 0 1 0 0 1 x x x 32 248000h to 24ffffh sa81 0 1 0 0 1 0 1 0 x x x 32 250000h to 257fffh sa82 0 1 0 0 1 0 1 1 x x x 32 258000h to 25ffffh sa83 0 1 0 0 1 1 0 0 x x x 32 260000h to 267fffh sa84 0 1 0 0 1 1 0 1 x x x 32 268000h to 26ffffh sa85 0 1 0 0 1 1 1 0 x x x 32 270000h to 277fffh sa86 0 1 0 0 1 1 1 1 x x x 32 278000h to 27ffffh sa87 0 1 0 1 0 0 0 0 x x x 32 280000h to 287fffh sa88 0 1 0 1 0 0 0 1 x x x 32 288000h to 28ffffh sa89 0 1 0 1 0 0 1 0 x x x 32 290000h to 297fffh sa90 0 1 0 1 0 0 1 1 x x x 32 298000h to 29ffffh sa91 0 1 0 1 0 1 0 0 x x x 32 2a0000h to 2a7fffh sa92 0 1 0 1 0 1 0 1 x x x 32 2a8000h to 2affffh sa93 0 1 0 1 0 1 1 0 x x x 32 2b0000h to 2b7fffh sa94 0 1 0 1 0 1 1 1 x x x 32 2b8000h to 2bffffh sa95 0 1 0 1 1 0 0 0 x x x 32 2c0000h to 2c7fffh sa96 0 1 0 1 1 0 0 1 x x x 32 2c8000h to 2cffffh sa97 0 1 0 1 1 0 1 0 x x x 32 2d0000h to 2d7fffh sa98 0 1 0 1 1 0 1 1 x x x 32 2d8000h to 2dffffh sa99 0 1 0 1 1 1 0 0 x x x 32 2e0000h to 2e7fffh sa100 0 1 0 1 1 1 0 1 x x x 32 2e8000h to 2effffh sa101 0 1 0 1 1 1 1 0 x x x 32 2f0000h to 2f7fffh sa102 0 1 0 1 1 1 1 1 x x x 32 2f8000h to 2fffffh sa103 0 1 1 0 0 0 0 0 x x x 32 300000h to 307fffh sa104 0 1 1 0 0 0 0 1 x x x 32 308000h to 30ffffh sa105 0 1 1 0 0 0 1 0 x x x 32 310000h to 317fffh sa106 0 1 1 0 0 0 1 1 x x x 32 318000h to 31ffffh sa107 0 1 1 0 0 1 0 0 x x x 32 320000h to 327fffh sa108 0 1 1 0 0 1 0 1 x x x 32 328000h to 32ffffh sa109 0 1 1 0 0 1 1 0 x x x 32 330000h to 337fffh sa110 0 1 1 0 0 1 1 1 x x x 32 338000h to 33ffffh sa111 0 1 1 0 1 0 0 0 x x x 32 340000h to 347fffh sa112 0 1 1 0 1 0 0 1 x x x 32 348000h to 34ffffh sa113 0 1 1 0 1 0 1 0 x x x 32 350000h to 357fffh sa114 0 1 1 0 1 0 1 1 x x x 32 358000h to 35ffffh sa115 0 1 1 0 1 1 0 0 x x x 32 360000h to 367fffh sa116 0 1 1 0 1 1 0 1 x x x 32 368000h to 36ffffh
mbm29qm12dh -60 15 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank b sa117 0 1 1 0 1 1 1 0 x x x 32 370000h to 377fffh sa118 0 1 1 0 1 1 1 1 x x x 32 378000h to 37ffffh sa119 0 1 1 1 0 0 0 0 x x x 32 380000h to 387fffh sa120 0 1 1 1 0 0 0 1 x x x 32 388000h to 38ffffh sa121 0 1 1 1 0 0 1 0 x x x 32 390000h to 397fffh sa122 0 1 1 1 0 0 1 1 x x x 32 398000h to 39ffffh sa123 0 1 1 1 0 1 0 0 x x x 32 3a0000h to 3a7fffh sa124 0 1 1 1 0 1 0 1 x x x 32 3a8000h to 3affffh sa125 0 1 1 1 0 1 1 0 x x x 32 3b0000h to 3b7fffh sa126 0 1 1 1 0 1 1 1 x x x 32 3b8000h to 3bffffh sa127 0 1 1 1 1 0 0 0 x x x 32 3c0000h to 3c7fffh sa128 0 1 1 1 1 0 0 1 x x x 32 3c8000h to 3cffffh sa129 0 1 1 1 1 0 1 0 x x x 32 3d0000h to 3d7fffh sa130 0 1 1 1 1 0 1 1 x x x 32 3d8000h to 3dffffh sa131 0 1 1 1 1 1 0 0 x x x 32 3e0000h to 3e7fffh sa132 0 1 1 1 1 1 0 1 x x x 32 3e8000h to 3effffh sa133 0 1 1 1 1 1 1 0 x x x 32 3f0000h to 3f7fffh sa134 0 1 1 1 1 1 1 1 x x x 32 3f8000h to 3fffffh
mbm29qm12dh -60 16 sector address table ( bank c ) (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa135 1 0 0 00000xxx 32 400 000h to 407fffh sa136 1 0 0 00001xxx 32 408000h to 40ffffh sa137 1 0 0 00010xxx 32 410 000h to 417fffh sa138 1 0 0 00011xxx 32 418000h to 41ffffh sa139 1 0 0 00100xxx 32 420 000h to 427fffh sa140 1 0 0 00101xxx 32 428000h to 42ffffh sa141 1 0 0 00110xxx 32 430 000h to 437fffh sa142 1 0 0 00111xxx 32 438000h to 43ffffh sa143 1 0 0 01000xxx 32 440 000h to 447fffh sa144 1 0 0 01001xxx 32 448000h to 44ffffh sa145 1 0 0 01010xxx 32 450 000h to 457fffh sa146 1 0 0 01011xxx 32 458000h to 45ffffh sa147 1 0 0 01100xxx 32 460 000h to 467fffh sa148 1 0 0 01101xxx 32 468000h to 46ffffh sa149 1 0 0 01110xxx 32 470 000h to 477fffh sa150 1 0 0 01111xxx 32 478000h to 47ffffh sa151 1 0 0 10000xxx 32 480 000h to 487fffh sa152 1 0 0 10001xxx 32 488000h to 48ffffh sa153 1 0 0 10010xxx 32 490 000h to 497fffh sa154 1 0 0 10011xxx 32 498000h to 49ffffh sa155 1 0 0 10100xxx 32 4a0 000h to 4a7fffh sa156 1 0 0 10101xxx 32 4a80 00h to 4affffh sa157 1 0 0 10110xxx 32 4b0 000h to 4b7fffh sa158 1 0 0 10111xxx 32 4b80 00h to 4bffffh sa159 1 0 0 11000xxx 32 4c0 000h to 4c7fffh sa160 1 0 0 11001xxx 32 4c80 00h to 4cffffh sa161 1 0 0 11010xxx 32 4d0 000h to 4d7fffh sa162 1 0 0 11011xxx 32 4d80 00h to 4dffffh sa163 1 0 0 11100xxx 32 4e0 000h to 4e7fffh sa164 1 0 0 11101xxx 32 4e80 00h to 4effffh sa165 1 0 0 11110xxx 32 4f0 000h to 4f7fffh sa166 1 0 0 11111xxx 32 4f80 00h to 4fffffh sa167 1 0 1 00000xxx 32 500 000h to 507fffh sa168 1 0 1 00001xxx 32 508000h to 50ffffh sa169 1 0 1 00010xxx 32 510 000h to 517fffh sa170 1 0 1 00011xxx 32 518000h to 51ffffh sa171 1 0 1 00100xxx 32 520 000h to 527fffh sa172 1 0 1 00101xxx 32 528000h to 52ffffh sa173 1 0 1 00110xxx 32 530 000h to 537fffh
mbm29qm12dh -60 17 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa174 1 0 1 0 0 1 1 1 x x x 32 538000h to 53ffffh sa175 1 0 1 0 1 0 0 0 x x x 32 540000h to 547fffh sa176 1 0 1 0 1 0 0 1 x x x 32 548000h to 54ffffh sa177 1 0 1 0 1 0 1 0 x x x 32 550000h to 557fffh sa178 1 0 1 0 1 0 1 1 x x x 32 558000h to 55ffffh sa179 1 0 1 0 1 1 0 0 x x x 32 560000h to 567fffh sa180 1 0 1 0 1 1 0 1 x x x 32 568000h to 56ffffh sa181 1 0 1 0 1 1 1 0 x x x 32 570000h to 577fffh sa182 1 0 1 0 1 1 1 1 x x x 32 578000h to 57ffffh sa183 1 0 1 1 0 0 0 0 x x x 32 580000h to 587fffh sa184 1 0 1 1 0 0 0 1 x x x 32 588000h to 58ffffh sa185 1 0 1 1 0 0 1 0 x x x 32 590000h to 597fffh sa186 1 0 1 1 0 0 1 1 x x x 32 598000h to 59ffffh sa187 1 0 1 1 0 1 0 0 x x x 32 5a0000h to 5a7fffh sa188 1 0 1 1 0 1 0 1 x x x 32 5a8000h to 5affffh sa189 1 0 1 1 0 1 1 0 x x x 32 5b0000h to 5b7fffh sa190 1 0 1 1 0 1 1 1 x x x 32 5b8000h to 5bffffh sa191 1 0 1 1 1 0 0 0 x x x 32 5c0000h to 5c7fffh sa192 1 0 1 1 1 0 0 1 x x x 32 5c8000h to 5cffffh sa193 1 0 1 1 1 0 1 0 x x x 32 5d0000h to 5d7fffh sa194 1 0 1 1 1 0 1 1 x x x 32 5d8000h to 5dffffh sa195 1 0 1 1 1 1 0 0 x x x 32 5e0000h to 5e7fffh sa196 1 0 1 1 1 1 0 1 x x x 32 5e8000h to 5effffh sa197 1 0 1 1 1 1 1 0 x x x 32 5f0000h to 5f7fffh sa198 1 0 1 1 1 1 1 1 x x x 32 5f8000h to 5fffffh sa199 1 1 0 0 0 0 0 0 x x x 32 600000h to 607fffh sa200 1 1 0 0 0 0 0 1 x x x 32 608000h to 60ffffh sa201 1 1 0 0 0 0 1 0 x x x 32 610000h to 617fffh sa202 1 1 0 0 0 0 1 1 x x x 32 618000h to 61ffffh sa203 1 1 0 0 0 1 0 0 x x x 32 620000h to 627fffh sa204 1 1 0 0 0 1 0 1 x x x 32 628000h to 62ffffh sa205 1 1 0 0 0 1 1 0 x x x 32 630000h to 637fffh sa206 1 1 0 0 0 1 1 1 x x x 32 638000h to 63ffffh sa207 1 1 0 0 1 0 0 0 x x x 32 640000h to 647fffh sa208 1 1 0 0 1 0 0 1 x x x 32 648000h to 64ffffh sa209 1 1 0 0 1 0 1 0 x x x 32 650000h to 657fffh sa210 1 1 0 0 1 0 1 1 x x x 32 658000h to 65ffffh sa211 1 1 0 0 1 1 0 0 x x x 32 660000h to 667fffh sa212 1 1 0 0 1 1 0 1 x x x 32 668000h to 66ffffh
mbm29qm12dh -60 18 (continued) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank c sa213 1 1 0 0 1 1 1 0 x x x 32 670000h to 677fffh sa214 1 1 0 0 1 1 1 1 x x x 32 678000h to 67ffffh sa215 1 1 0 1 0 0 0 0 x x x 32 680000h to 687fffh sa216 1 1 0 1 0 0 0 1 x x x 32 688000h to 68ffffh sa217 1 1 0 1 0 0 1 0 x x x 32 690000h to 697fffh sa218 1 1 0 1 0 0 1 1 x x x 32 698000h to 69ffffh sa219 1 1 0 1 0 1 0 0 x x x 32 6a0000h to 6a7fffh sa220 1 1 0 1 0 1 0 1 x x x 32 6a8000h to 6affffh sa221 1 1 0 1 0 1 1 0 x x x 32 6b0000h to 6b7fffh sa222 1 1 0 1 0 1 1 1 x x x 32 6b8000h to 6bffffh sa223 1 1 0 1 1 0 0 0 x x x 32 6c0000h to 6c7fffh sa224 1 1 0 1 1 0 0 1 x x x 32 6c8000h to 6cffffh sa225 1 1 0 1 1 0 1 0 x x x 32 6d0000h to 6d7fffh sa226 1 1 0 1 1 0 1 1 x x x 32 6d8000h to 6dffffh sa227 1 1 0 1 1 1 0 0 x x x 32 6e0000h to 6e7fffh sa228 1 1 0 1 1 1 0 1 x x x 32 6e8000h to 6effffh sa229 1 1 0 1 1 1 1 0 x x x 32 6f0000h to 6f7fffh sa230 1 1 0 1 1 1 1 1 x x x 32 6f8000h to 6fffffh
mbm29qm12dh -60 19 sector address table ( bank d ) bank sector sector address sector size (kwords) ( 16) address range bank address a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 bank d sa231 1 1 1 00000xxx 32 700 000h to 707fffh sa232 1 1 1 00001xxx 32 708000h to 70ffffh sa233 1 1 1 00010xxx 32 710 000h to 717fffh sa234 1 1 1 00011xxx 32 718000h to 71ffffh sa235 1 1 1 00100xxx 32 720 000h to 727fffh sa236 1 1 1 00101xxx 32 728000h to 72ffffh sa237 1 1 1 00110xxx 32 730 000h to 737fffh sa238 1 1 1 00111xxx 32 738000h to 73ffffh sa239 1 1 1 01000xxx 32 740 000h to 747fffh sa240 1 1 1 01001xxx 32 748000h to 74ffffh sa241 1 1 1 01010xxx 32 750 000h to 757fffh sa242 1 1 1 01011xxx 32 758000h to 75ffffh sa243 1 1 1 01100xxx 32 760 000h to 767fffh sa244 1 1 1 01101xxx 32 768000h to 76ffffh sa245 1 1 1 01110xxx 32 770 000h to 777fffh sa246 1 1 1 01111xxx 32 778000h to 77ffffh sa247 1 1 1 10000xxx 32 780 000h to 787fffh sa248 1 1 1 10001xxx 32 788000h to 78ffffh sa249 1 1 1 10010xxx 32 790 000h to 797fffh sa250 1 1 1 10011xxx 32 798000h to 79ffffh sa251 1 1 1 10100xxx 32 7a0 000h to 7a7fffh sa252 1 1 1 10101xxx 32 7a80 00h to 7affffh sa253 1 1 1 10110xxx 32 7b0 000h to 7b7fffh sa254 1 1 1 10111xxx 32 7b80 00h to 7bffffh sa255 1 1 1 11000xxx 32 7c0 000h to 7c7fffh sa256 1 1 1 11001xxx 32 7c80 00h to 7cffffh sa257 1 1 1 11010xxx 32 7d0 000h to 7d7fffh sa258 1 1 1 11011xxx 32 7d80 00h to 7dffffh sa259 1 1 1 11100xxx 32 7e0 000h to 7e7fffh sa260 1 1 1 11101xxx 32 7e80 00h to 7effffh sa261 1 1 1 11110xxx 32 7f0 000h to 7f7fffh sa262 1 1 1 11111000 4 7f8 000h to 7f8fffh sa263 1 1 1 11111001 4 7f9 000h to 7f9fffh sa264 1 1 1 11111010 4 7fa 000h to 7fafffh sa265 1 1 1 11111011 4 7fb 000h to 7fbfffh sa266 1 1 1 11111100 4 7fc 000h to 7fcfffh sa267 1 1 1 11111101 4 7fd 000h to 7fdfffh sa268 1 1 1 11111110 4 7fe 000h to 7fefffh sa269 1 1 1 11111111 4 7ff 000h to 7fffffh
mbm29qm12dh -60 20 sector group address table (continued) sector group a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga0 00000000000 sa0 sga1 00000000001 sa1 sga2 00000000010 sa2 sga3 00000000011 sa3 sga4 00000000100 sa4 sga5 00000000101 sa5 sga6 00000000110 sa6 sga7 00000000111 sa7 sga8 00000001xxx sa8 sga9 00000010xxx sa9 sga10 00000011xxx sa10 sga11 0 0 0 0 0 1 x x x x x sa11 to sa14 sga12 0 0 0 0 1 0 x x x x x sa15 to sa18 sga13 0 0 0 0 1 1 x x x x x sa19 to sa22 sga14 0 0 0 1 0 0 x x x x x sa23 to sa26 sga15 0 0 0 1 0 1 x x x x x sa27 to sa30 sga16 0 0 0 1 1 0 x x x x x sa31 to sa34 sga17 0 0 0 1 1 1 x x x x x sa35 to sa38 sga18 0 0 1 0 0 0 x x x x x sa39 to sa42 sga19 0 0 1 0 0 1 x x x x x sa43 to sa46 sga20 0 0 1 0 1 0 x x x x x sa47 to sa50 sga21 0 0 1 0 1 1 x x x x x sa51 to sa54 sga22 0 0 1 1 0 0 x x x x x sa55 to sa58 sga23 0 0 1 1 0 1 x x x x x sa59 to sa62 sga24 0 0 1 1 1 0 x x x x x sa63 to sa66 sga25 0 0 1 1 1 1 x x x x x sa67 to sa70 sga26 0 1 0 0 0 0 x x x x x sa71 to sa74 sga27 0 1 0 0 0 1 x x x x x sa75 to sa78
mbm29qm12dh -60 21 (continued) sector group a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga28 0 1 0 0 1 0 x x x x x sa79 to sa82 sga29 0 1 0 0 1 1 x x x x x sa83 to sa86 sga30 0 1 0 1 0 0 x x x x x sa87 to sa90 sga31 0 1 0 1 0 1 x x x x x sa91 to sa94 sga32 0 1 0 1 1 0 x x x x x sa95 to sa98 sga33 0 1 0 1 1 1 x x x x x sa99 to sa102 sga34 0 1 1 0 0 0 x x x x x sa103 to sa106 sga35 0 1 1 0 0 1 x x x x x sa107 to sa110 sga36 0 1 1 0 1 0 x x x x x sa111 to sa114 sga37 0 1 1 0 1 1 x x x x x sa115 to sa118 sga38 0 1 1 1 0 0 x x x x x sa119 to sa122 sga39 0 1 1 1 0 1 x x x x x sa123 to sa126 sga40 0 1 1 1 1 0 x x x x x sa127 to sa130 sga41 0 1 1 1 1 1 x x x x x sa131 to sa134 sga42 1 0 0 0 0 0 x x x x x sa135 to sa138 sga43 1 0 0 0 0 1 x x x x x sa139 to sa142 sga44 1 0 0 0 1 0 x x x x x sa143 to sa146 sga45 1 0 0 0 1 1 x x x x x sa147 to sa150 sga46 1 0 0 1 0 0 x x x x x sa151 to sa154 sga47 1 0 0 1 0 1 x x x x x sa155 to sa158 sga48 1 0 0 1 1 0 x x x x x sa159 to sa162 sga49 1 0 0 1 1 1 x x x x x sa163 to sa166 sga50 1 0 1 0 0 0 x x x x x sa167 to sa170 sga51 1 0 1 0 0 1 x x x x x sa171 to sa174
mbm29qm12dh -60 22 (continued) sector group a 22 a 21 a 20 a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 sectors sga52 1 0 1 0 1 0 x x x x x sa175 to sa178 sga53 1 0 1 0 1 1 x x x x x sa179 to sa182 sga54 1 0 1 1 0 0 x x x x x sa183 to sa186 sga55 1 0 1 1 0 1 x x x x x sa187 to sa190 sga56 1 0 1 1 1 0 x x x x x sa191 to sa194 sga57 1 0 1 1 1 1 x x x x x sa195 to sa198 sga58 1 1 0 0 0 0 x x x x x sa199 to sa202 sga59 1 1 0 0 0 1 x x x x x sa203 to sa206 sga60 1 1 0 0 1 0 x x x x x sa207 to sa210 sga61 1 1 0 0 1 1 x x x x x sa211 to sa214 sga62 1 1 0 1 0 0 x x x x x sa215 to sa218 sga63 1 1 0 1 0 1 x x x x x sa219 to sa222 sga64 1 1 0 1 1 0 x x x x x sa223 to sa226 sga65 1 1 0 1 1 1 x x x x x sa227 to sa230 sga66 1 1 1 0 0 0 x x x x x sa231 to sa234 sga67 1 1 1 0 0 1 x x x x x sa235 to sa238 sga68 1 1 1 0 1 0 x x x x x sa239 to sa242 sga69 1 1 1 0 1 1 x x x x x sa243 to sa246 sga70 1 1 1 1 0 0 x x x x x sa247 to sa250 sga71 1 1 1 1 0 1 x x x x x sa251 to sa254 sga72 1 1 1 1 1 0 x x x x x sa255 to sa258 sga73 1 1 1 1 1 1 0 0 x x x sa259 sga74 1 1 1 1 1 1 0 1 x x x sa260 sga75 1 1 1 1 1 1 1 0 x x x sa261 sga76 11111111000 sa262 sga77 11111111001 sa263 sga78 11111111010 sa264 sga79 11111111011 sa265 sga80 11111111100 sa266 sga81 11111111101 sa267 sga82 11111111110 sa268 sga83 11111111111 sa269
mbm29qm12dh -60 23 common flash memory interface code table description a 6 to a 0 dq 15 to dq 0 query-unique ascii string qry 10h 11h 12h 0051h 0052h 0059h primary oem command set 02h: amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min voltage (write/erase) dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 1bh 0027h v cc max voltage (write/erase) dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 1ch 0036h v pp min voltage 1dh 0000h v pp max voltage 1eh 0000h typical timeout per single byte/word write 2 n m s 1fh 0004h typical timeout for min size buffer write 2 n m s 20h 0000h typical timeout per individual block erase 2 n ms 21h 0009h typical timeout for full chip erase 2 n ms 22h 0000h max timeout for byte/word write 2 n times typical 23h 0005h max timeout for buffer write 2 n times typical 24h 0000h max timeout per individual block erase 2 n times typical 25h 0004h max timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0018h flash device interface description 01h : 16 28h 29h 0001h 0000h max number of byte in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0003h erase block region 1 information 2dh 2eh 2fh 30h 0007h 0000h 0020h 0000h erase block region 2 information 31h 32h 33h 34h 00fdh 0000h 0000h 0001h erase block region 3 information 35h 36h 37h 38h 0007h 0000h 0020h 0000h description a 6 to a 0 dq 15 to dq 0 erase block region 4 information 39h 3ah 3bh 3ch 0000h 0000h 0000h 0000h query-unique ascii string pri 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0033h address sensitive unlock ch = required and 0.13 m m technology dh = not required and 0.13 m m technology 45h 000ch erase suspend 02h = to read & write 46h 0002h sector protection 00h = not supported x = number of sectors in per group 47h 0001h sector temporary unprotection 01h = supported 48h 0001h sector protection algorithm 49h 0007h simultaneous operation 00h = not supported, x = total number of sectors in all banks except bank a 4ah 00e7h burst mode type 00h = not supported 4bh 0000h page mode type 00h = not supported 4ch 0002h v acc (acceleration) supply minimum 00h = not supported, dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 4dh 0085h v acc (acceleration) supply maximum 00h = not supported, dq 7 to dq 4 : 1 v, dq 3 to dq 0 : 100 mv 4eh 0095h boot type 4fh 0001h program suspend 01h = supported 50h 0001h bank organization 57h 0004h bank a region information 58h 0027h bank b region information 59h 0060h bank c region information 5ah 0060h bank d region information 5bh 0027h
mbm29qm12dh -60 24 n functional description simultaneous operation the device features functions that enable reading of data from one memory bank while a program or erase operation is in progress in the other memory bank (simultaneous operation) , in addition to conventional features (read, program, erase, erase-suspend read, and erase-suspend program) . the bank can be selected by bank address (a 22 , a 21 , a 20 ) with zero latency. the device consists of the following four banks : bank a : 8 4 kw and 31 32 kw; bank b : 96 32 kw; bank c : 96 32 kw; bank d : 8 4 kw and 31 32 kw. the device can execute simultaneous operations between bank 1, a bank chosen from among the four banks, and bank 2, a bank consisting of the three remaining banks. (see flexbank tm architecture table in n func- tional description.) this is what we call a flexbank, for example, the rest of banks b, c and d to let the system read while bank a is in the process of program (or erase) operation. however, the different types of operations for the three banks are impossible, e.g. bank a writing, bank b erasing, and bank c reading out. with this flexbank, as described in example of virtual banks combination table in n functional de- scription, the system gets to select from four combinations of data volume for bank 1 and bank 2, which works well to meet the system requirement. the simultaneous operation cannot execute multi-function mode in the same bank. simultaneous operation table in n functional description shows the possible com- binations for simultaneous operation. (refer to bank-to-bank read/write timing diagram in n timing dia- gram.) flexbank tm architecture table example of virtual banks combination table note : when multiple sector erase over several banks is operated, the system cannot read out of the bank to which a sector being erased belongs. for example, suppose that erasing is taking place at both bank a and bank b, neither bank a nor bank b is read out (they would output the sequence flag once they were selected.) meanwhile the system would get to read from either bank c or bank d. bank splits bank 1 bank 2 volume combination volume combination 1 16 mbit bank a 112 mbit remainder (bank b, c, d) 2 48 mbit bank b 80 mbit remainder (bank a, c, d) 3 48 mbit bank c 80 mbit remainder (bank a, b, d) 4 16 mbit bank d 112 mbit remainder (bank a, b, c) bank splits bank 1 bank 2 volume combination sector size volume combination sector size 1 16 mbit bank a 8 4 kwords + 31 32 kwords 112 mbits bank b + bank c + bank d 8 4 kwords + 223 32 kwords 2 32 mbit bank a + bank d 16 4 kwords + 62 32 kwords 96 mbits bank b + bank c 192 32 kwords 3 48 mbit bank b 96 32 kwords 80 mbits bank a + bank c + bank d 16 4 kwords + 158 32 kwords 4 64 mbit bank a + bank b 8 4 kwords + 127 32 kwords 64 mbits bank c + bank d 8 4 kwords + 127 32 kwords
mbm29qm12dh -60 25 simultaneous operation table note : bank 1 and bank 2 are divided for the sake of convenience at simultaneous operation. actually, the bank consists of 4 banks, bank a, bank b, bankc and bank d. bank address (ba) means to specify each of the banks. read mode the device has two control functions which are required in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins. address access time (t acc ) is equal to delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the delay from the falling edge of oe to valid data at the output pins (assuming the addresses have been stable for at least t acc - t oe time) . when reading out data without changing addresses after power- up, it is necessary to input hardware reset or to change ce pin from h or l page mode read the device is capable of fast page mode read. this mode provides faster read access speed by sequential access within a page. the page size of the device is 8 words, within the appropriate page being selected by the higher address bits a 22 to a 3 and the lsb bits a 2 to a 0 determining the specific word within that page. this is an asynchronous operation with the microprocessor supplying the specific word location. the random or initial page access is equal to t acc and subsequent page read access (as long as the locations specified by the microprocessor fall within that page) is equivalent to t pa c c . here again, ce selects the device and oe is the output control and should be used to gate data to the output pins if the device is selected. fast page mode accesses are obtained by keeping a 22 to a 3 constant and changing a 2 to a 0 within that page. standby mode there are two ways to implement the standby mode on the device, one using both the ce and reset pins, and the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset input held at v cc 0.3 v. under this condition the current consumed is less than 5 a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even if ce = h. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with reset input held at v ss 0.3 v (ce = h or l) . under this condition the current consumed is less than 5 a max. once the reset pin is set high, the device requires t rh as a wake-up time for output to be valid for read access. during standby mode, the output is in the high impedance state, regardless of oe input. case bank 1 status bank 2 status 1 read mode read mode 2 read mode autoselect mode 3 read mode program mode 4 read mode erase mode 5 autoselect mode read mode 6 program mode read mode 7 erase mode read mode
mbm29qm12dh -60 26 automatic sleep mode automatic sleep mode works to restrain power consumption during read-out of device data. it can be useful in applications such as handy terminal, which requires low power consumption. to activate this mode, the device automatically switches itself to low power mode when the device addresses remain stable during access time of 150 ns. it is not necessary to control ce , we and oe in this mode. in this mode the current consumed is typically 1 a (cmos level) . during simultaneous operation, v cc active current (i cc2 ) is required. since the data are latched during this mode, the data are continuously read out. when the addresses are changed, the mode is automatically canceled and the device reads the data for changed addresses. output disable with the oe input at a logic high level (v ih ) , output from the device is disabled. this will cause the output pins to be in a high impedance state. autoselect the autoselect mode allows the reading out of a binary code and identifies its manufacturer and type.it is intended for use by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id on address pin a 9 . three identifier bytes may then be sequenced from the device outputs by toggling addresses. all addresses are dont cares except a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 and a 0 . (see mbm29qm12dh user bus operations table and mbm29qm12dh com- mand definitions table in n device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the device is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illustrated in mbm29qm12dh command definitions table in n device bus operation. (refer to au- toselect command section.) in the command autoselect mode, the bank addresses ba;(a 22 , a 21 , a 20 ) must point to a specific bank during the third write bus cycle of the autoselect command. then the autoselect data will be read from that bank while array data can be read from the other bank. in word mode, a read cycle from address 00h returns the manufacturers code (fujitsu = 04h) . a read cycle at address 01h outputs device code. when 227eh is output, it indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at addresses of 0eh and 0fh. (refer to mbm29qm12dh sector group protection verify autoselect codes table and extended autoselect code table in n device bus operation ) in the case of applying v id on a 9 , since both bank 1 and bank 2 enter autoselect mode, simultanous operation cannot be executed. write device erasure and programming are accomplished via the command register. the contents of the register serve as input to the internal state machine. the state machine output dictates the function of the device. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the com- mand register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of we or ce , whichever happens later, while data is latched on the rising edge of we or ce , whichever happens first. standard microprocessor write timings are used. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. accelerated program operation the device offers accelerated program operation which enables the programming in high speed. if the system asserts v acc to the wp /acc pin, the device automatically enters the acceleration mode and the time required
mbm29qm12dh -60 27 for program operation will reduce to about 60%. this function is primarily intended to allow high speed program, so caution is needed as the sector group will temporarily be unprotected. the system would use a fast program command sequence when programming during acceleration mode. set command to fast mode and reset command from fast mode are not necessary. when the device enters the acceleration mode, the device automatically set to fast mode. therefore, the pressent sequence could be used for programming and detection of completion during acceleration mode. removing v acc from the wp /acc pin returns the device to normal operation. do not remove v acc from wp / acc pin while programming. see accelerated program timing diagram in n timing diagram. reset hardware reset the device may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least t rp in order to properly reset the internal state machine. any operation in the process of being executed will be terminated and the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high the device requires an additional t rh before it will allow read access. when the reset pin is low, the device will be in the standby mode for the duration of the pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operation, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. see reset , ry/by timing diagram in n timing diagram for the timing diagram. refer to temporary sector group unprotection for additional functionality. boot block sector protection the write protection function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp /acc pin. if the system asserts v il on the wp /acc pin, the device disables program and erase functions in the two outermost 8k bytes on both ends of boot sectors (sa0, sa1, sa268, sa269) independently of whether those sectors are protected or unprotected using the method described in sector group protection. if the system asserts v ih on the wp /acc pin, the device reverts to whether the two outermost 8k byte on both ends of boot sectors ware last set to be protected or unprotected. sector group protection or unprotection for these four sectors depends on whether they ware last protected or unprotected using the method described in sector group protection. hiddenrom region the hiddenrom feature provides a flash memory region that the system may access through a new command sequence. this is primarily intended for customers who wish to use an electronic serial number (esn) in the device with the esn protected against modification. once the hiddenrom region is protected, any further modification of that region becomes impossible. this ensures the security of the esn once the product is shipped to the field. only program is possible in this area until it is protected. once it is protected, it is impossible to unprotect, so please use this with caution. hiddenrom area is 128 words (64 words for factory and 64 words for customer) in length and is stored at the same address of the "outermost" 4 kwords boot sector. the device occupies the address of the 000000h to 00007fh. after the system has written the enter hiddenrom command sequence, the system may read the hiddenrom region by using the addresses normally occupied by the boot sector (particular area of sa0). that is, the device sends all commands that would normally be sent to the boot sector to the hiddenrom region. this mode of operation continues until the system issues the exit hiddenrom command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sector. hiddenrom area is devided into two regions, which are factory locked area and customer locked area. the factory locked area is 64 words (address: 000000h to 00003fh) that is programmed and locked at fujitsu. the customer locked area is also 64 words (address: 000040h to 00007fh) that is programmed and locked at user. the factory indicator bit (dq 7 ) is used to indicate whether or not the factory locked area is locked when shipped from the factory. the customer indicator bit (dq 6 ) is used to indicate whether or not the customer locked area is locked. the factory locked area can be programmed and protected at fujitsu only and is always protected
mbm29qm12dh -60 28 when shipped from the factory regardless of the conditon whether or not this area is programmed. therefore this area has the factory indicator bit (dq 7 ) permanently set to a "1". the factory locked area cannot be modified in any way. the customer locked area is shipped unprotected, allowing users to utilize that area in any manner they choose. the customer indicator bit set to "0". once the customer locked area is protected, the customer indicator bit will be permanently set to "1". (3) extended sector group protection [software protection] in addition to normal sector group protection, the device has extended sector group protection as extended function. this function enables protection of the sector group by forcing v id on reset pin and writes a command sequence. unlike conventional procedures, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector group protection in this mode. the extended sector group protection requires v id on reset pin. with this condition the operation is initiated by writing the set-up command (60h) in the command register. then the sector group addresses pins (a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 0, 0, 0, 1, 0) should be set to the sector group to be protected (setting v il for the other addresses pins is recommended) , and an extended sector group protection command (60h) should be written. a sector group is typically protected in 250 m s. to verify programming of the protection circuitry, the sector group addresses pins (a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 0, 0, 0, 1, 0) should be set a command (40h) should be written. following the command write, a logical 1 at device output dq 0 will produce a protected sector in the read operation. if the output is logical 0, write the extended sector group protection command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . (refer to extended sector gropup protection timing diagram in n timing diagram and extended sector group protection algorithm in n flow chart.) if persistent protection bit lock is set to "1", this mode is disabled. (4) new sector protection [software protection] a command sector protection method that replaces the old v id controlled protection method in future. however mbm29qm12dh support both v id protection and persistent sector protection. both protect supported as a shift period. the persistent sector protection and the old v id controlled protection can go back each other until persistent protection lock bit is settled. a) persistent protection bit (ppb) a single persistent (non-volatile) protection bit is assigned to a maximum four sectors (see the sector address tables for specific sector protection groupings). all 4 k words boot-block sectors have individual sector persistent protection bits (ppbs) for greater flexibility. each ppb is individually modifiable through the ppb write command. note: if a ppb requires erasure, all of the sector ppbs must first be preprogrammed prior to ppb erasing. all ppbs erase in parallel, unlike programming where individual ppbs are programmable. it is the responsibility of the user to perform the preprogramming operation. otherwise, an already erased sector ppbs has the potential of being over-erased. there is no hardware mechanism to prevent sector ppbs over-erasure. b) dynamic protection bit (dpb) a volatile protection bit is assigned for each sector. after power-up or hardware reset, the contents of all dpbs is 0. each dpb is individually modifiable through the dpb write command. when the parts are first shipped, the ppbs are cleared, the dpbs are cleared, and ppb lock is defaulted to power up in the cleared state - meaning the ppbs are changeable. when the device is first powered on the dpbs power up cleared (sectors not protected). the protection state for each sector is determined by the logical or of the ppb and the dpb related to that sector. for the sectors that have the ppbs cleared, the dpbs control whether or not the sector is protected or unprotected. by issuing the dpb write/erase command sequences, the dpbs will be set or cleared, thus placing each sector in the protected or unprotected state. these are the so-called dynamic locked or unlocked states. they are called dynamic states because it is very easy to switch back and forth between the protected and unprotected conditions. this allows software to easily protect sectors against inadvertent changes yet does not prevent the easy removal of protection when changes are needed. the dpbs maybe set or cleared as often as needed.
mbm29qm12dh -60 29 ppb vs dpb the ppbs allow for a more static, and difficult to change, level of protection. the ppbs retain their state across power cycles because they are non-volatile. individual ppbs are set with a command but must all be cleared as a group through a complex sequence of program and erasing commands. the ppbs are also limited to 100 erase cycles. the pbb lock bit adds an additional level of protection. once all ppbs are programmed to the desired settings, the ppb lock may be set to 1. setting the ppb lock disables all program and erase commands to the non- volatile ppbs. in effect, the ppb lock bit locks the ppbs into their current state. the only way to clear the ppb lock is to go through a power cycle. system boot code can determine if any changes to the ppb are needed e.g. to allow new system code to be downloaded. if no changes are needed then the boot code can set the pbb lock to disable any further changes to the pbbs during system operation. the wp /acc write protect pin adds a final level of hardware protection to the two outermost 4 kwords sectors. when this pin is low it is not possible to change the contents of these two sectors. these sectors generally hold system boot code. so, the wp /acc pin can prevent any changes to the boot code that could override the choices made while setting up sector protection during system initialization. it is possible to have sectors that have been persistently locked, and sectors that are left in the dynamic state. the sectors in the dynamic state are all unprotected. if there is a need to protect some of them, a simple dpb write command sequence is all that is necessary. the dpb write/erase command for the dynamic sectors switch the dpbs to signify protected and unprotected, respectively. if there is a need to change the status of the persistently locked sectors, a few more steps are required. first, the ppb lock bit must be disabled by either putting the device through a power-cycle, or hardware reset. the ppbs can then be changed to reflect the desired settings. setting the ppb lock bit once again will lock the ppbs, and the device operates normally again. note: to achieve the best protection, its recommended to execute the ppb lock bit set command early in the boot code, and protect the boot code by holding wp /acc = v il . the above table contains all possible combinations of the dpb, ppb, and ppb lock relating to the status of the sector. in summary, if the ppb is set, and the ppb lock is set, the sector is protected and the protection can not be removed until the next power cycle clears the pbb lock. if the ppb is cleared, the sector can be dynamically locked or unlocked. the dpb then controls whether or not the sector is protected or unprotected. if the user attempts to program or erase a protected sector, the device ignores the command and returns to read mode. a program command to a protected sector enables status polling for approximately 1 m s before the device returns to read mode without having modified the contents of the protected sector. an erase command to a protected sector enables status polling for approximately 50 m s after which the device returns to read mode without having erased the protected sector. the programming of the dpb, ppb, and ppb lock for a given sector can be verified by writing a dpb/ppb lock verify command to the device. dpb ppb ppb lock sector state 000unprotected ppb and dpb are changeable 100protected ppb and dpb are changeable 010protected ppb and dpb are changeable 110protected ppb and dpb are changeable 001 unprotected ppb is not changeable, dpb is changeable 101protected ppb is not changeable, dpb is changeable 011protected ppb is not changeable, dpb is changeable 111protected ppb is not changeable, dpb is changeable
mbm29qm12dh -60 30 Cdpb status the programming of the dpb for a given sector can be verified by writing a dpb status verify command to the device. Cppb status the programming of the ppb for a given sector can be verified by writing a ppb status verify command to the device. Cppb lock bit status the programming of the ppb lock bit for a given sector can be verified by writing a ppb lock bit status verify command to the device. c) persistent protection bit lock (ppb lock) ? ppb locked ? ppb locked with password a highly sophisticated protection method that requires a password before changes to certain sectors or sector groups are permitted. all parts default to operate in the persistent sector protection mode. the customer must then choose if the persistent or password protection method is most desirable. there are two one-time programmable non-volatile bits that define which sector protection method will be used. if the customer decides to continue using the persistent sector protection method, they must set the persistent sector protection mode locking bit. this will permanently set the part to operate only using persistent sector protection. if the customer decides to use the password method, they must set the password mode locking bit. this will permanently set the part to operate only using password sector protection. it is important to remember that setting either the persistent sector protection mode locking bit or the password mode locking bit permanently selects the protection mode. it is not possible to switch between the two methods once a locking bit has been set. it is important that one mode is explicitly selected when the device is first programmed, rather than relying on the default mode alone. this is so that it is not possible for a system program or virus to later set the password mode locking bit, which would cause an unexpected shift from the default persistent sector protection mode into the password protection mode. the wp /acc hardware protection feature is always available, independent of the software managed protection method chosen. a global volatile bit. when set to 1, the ppbs cannot be changed. when cleared (0), the ppbs are changeable. there is only one ppb lock bit per device. the ppb lock is cleared after power-up or hardware reset. there is no command sequence to unlock the ppb lock. the persistent protection bit (ppb) lock is a volatile bit that reflects the state of the password mode locking bit after power-up reset. if the password mode locking bit is set, which indicates the device is in password protection mode, the ppb lock bit is also set after a hardware reset (reset asserted) or a power-up reset. the only means for clearing the ppb lock bit in password protection mode is to issue the password unlock command. successful execution of the password unlock command clears the ppb lock bit, allowing for sector ppbs modifications. asserting reset , taking the device through a power-on reset, or issuing the ppb lock bit set command sets the ppb lock bit back to a 1. if the password mode locking bit is not set, indicating persistent sector protection mode, the ppb lock bit is cleared after power-up or hardware reset. the ppb lock bit is set by issuing the ppb lock bit set command. once set the only means for clearing the ppb lock bit is by issuing a hardware or power-up reset. the password unlock command is ignored in persistent sector protection mode.
mbm29qm12dh -60 31 -password and password mode locking bit in order to select the password sector protection scheme, the customer must first program the password. fujitsu recommends that the password be somehow correlated to the unique electronic serial number (esn) of the particular flash device. each esn is different for every flash device; therefore each password should be different for every flash device. while programming in the password region, the customer may perform password verify operations. once the desired password is programmed in, the customer must then set the password mode locking bit. this operation achieves two objectives: (1) it permanently sets the device to operate using the password protection mode. it is not possible to reverse this function. (2) it also disables all further commands to the password region. all program, and read operations are ignored. both of these objectives are important, and if not carefully considered, may lead to unrecoverable errors. the user must be sure that the password protection method is desired when setting the password mode locking bit. more importantly, the user must be sure that the password is correct when the password mode locking bit is set. due to the fact that read operations are disabled, there is no means to verify what the password is afterwards. if the password is lost after setting the password mode locking bit, there will be no way to clear the ppb lock bit. the password mode locking bit, once set, prevents reading the 64-bit password on the dq bus and further password programming. the password mode locking bit is not erasable. once password mode locking bit is programmed, the persistent sector protection locking bit is disabled from programming, guaranteeing that no changes to the protection scheme are allowed. 64-bit password the 64-bit password is located in its own memory space and is accessible through the use of the password program and verify commands (see password verify command). the password function works in conjunction with the password mode locking bit, which when set, prevents the password verify command from reading the contents of the password on the pins of the device. -persistent sector protection mode locking bit like the password mode locking bit, a persistent sector protection mode locking bit exists to guarantee that the device remain in software sector protection. once set, the persistent sector protection locking bit prevents programming of the password protection mode locking bit. this guarantees that a hacker could not place the device in password protection mode. (5) temporary sector group unprotection this feature allows temporary unprotection of previously protected sectors of the device in order to change data. the sector unprotection mode is activated by setting the reset pin to high voltage (v id ). during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once the v id is taken away from the reset pin, all the previously protected sector groups will be protected again. while ppb lock is set, this device cannot enter the temporary sector unprotection mode.
mbm29qm12dh -60 32 n command definition device operations are selected by writing specific address and data sequences into the command register. some commands require bank address (ba) input. when command sequences are input into a bank reading, the commands have priority over the reading. mbm29qm12dh command definitions table in n device bus operation shows the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. also the program suspend (b0h) and program resume (30h) commands are valid only while the program operation is in progress. moreover, read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. writing incorrect address and data values or writing them in the improper sequence will take the device into unknow state. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read/reset mode, the read/ reset operation is initiated by writing the read/reset command sequence into the command register. micro- processor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case a command sequence is not required in order to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to ac read char- acteristics and timing diagram for the specific timing parameters. autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. therefore, manufacture and device codes must be accessible while the device resides in the target system. prom pro- grammers typically access the signature codes by raising a 9 to a higher voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming method- ology. the operation is initiated by writing the autoselect command sequence into the command register. the autoselect command sequence is initiated first by writing two unlock cycles. this is followed by a third write cycle that contains the bank address (ba) and the autoselect command. then the manufacture and device codes can be read from the bank, and actual data from the memory cell can be read from another bank. the higher order address (a 22 , a 21 , a 20 ) required for reading out the manufacture and device codes demands the bank address (ba) set at the third write cycle. following the command write, in word mode, a read cycle from address (ba) 00h returns the manufacturers code (fujitsu = 04h) . and a read cycle at address (ba) 01h outputs device code. when 227eh was output, this indicates that two additional codes, called extended device codes will be required. therefore the system may continue reading out these extended device codes at the address of (ba) 0eh, as well as at (ba) 0fh. notice that the above applies to word mode. (refer to mbm29qm12dh sector group protection verify autoselect codes table and extended autoselect code table in n device bus operation ) the sector state (ppb protection or ppb unprotection) will be informed by address (ba) xx02h for 16 . scanning the sector group addresses (a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while(a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 ,a 0 ) = (0, 0, 0, 0, 0, 0, 1, 0) will produce a logical 1 at device output dq 0 for a protected sector group. the programming verification should be performed by verifying sector group protection on the protected sector. (see mbm29qm12dh user bus operations table and mbm29qm12dh command definitions table in n device bus operation.) the manufacture and device codes can be read from the selected bank. to read the manufacture and device codes and sector protection status from a non-selected bank, it is necessary to write the read/reset command sequence into the register. autoselect command should then be written into the bank to be read. if the software (program code) for autoselect command is stored in the flash memory, the device and manu- facture codes should be read from the other bank, which does not contain the software.
mbm29qm12dh -60 33 to terminate the operation, it is necessary to write the read/reset command sequence into the register. to execute the autoselect command during the operation, read/reset command sequence must be written before the autoselect command. word programming command the device is programmed on a word-by-word basis. programming is a four bus cycle operation. there are two unlock write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later, and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of ce or we (whichever happens first) starts programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. the system can determine the status of the program operation by using dq 7 (data polling) , dq 6 (toggle bit) or ry/by . the data polling and toggle bit must be performed at the memory location which is being programmed. the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see hardware sequence flags table in n command definition). therefore, the device requires that a valid address to the device be supplied by the system in this particular instance. hence, data polling must be performed at the memory location which is being programmed. if hardware reset occurs during the programming operation, the data being written is not guaranteed. programming is allowed in any sequence and across sector boundaries. beware that a data 0 cannot be programmed back to a 1. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm but a read from read/reset mode will show that the data is still 0. only erase operations can convert from 0s to 1s. embedded erase tm algorithm in n flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. program suspend/resume command the program suspend command allows the system to interrupt a program operation so that data can be read from any address. writing the program suspend command (b0h) during the embedded program operation immediately suspends the programming. the program suspend command may also be issued during a pro- gramming operation while an erase is suspended. the bank addresses of sector being programmed should be set when writing the program suspend command. when the program suspend command is written during a programming process, the device halts the program operation within 1 s and updates the status bits. after the program operation has been suspended, the system can read data from any address. the data at program-suspended address is not valid. normal read timing and command definitions apply. after the program resume command (30h) is written, the device reverts to programming. the bank addresses of sectors being suspended should be set when writing the program resume command. the system can determine the status of the program operation using the dq 7 or dq 6 status bits, just as in the standard program operation. see write operation status for more information. the system may also write the autoselect command sequence when the device in the program suspend mode. the device allows reading autoselect codes at the addresses within programming sectors, since the codes are not stored in the memory. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the program resume command (address bits are bank address) to exit from the program suspend mode and continue the programming operation. further writes of the resume command are ignored. another program suspend command can be written after the device has resumed programming.
mbm29qm12dh -60 34 chip erase command chip erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequence, the device will automatically program and verify the entire memory for an all- zero data pattern prior to electrical erase (preprogram function) . the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) , dq 6 (toggle bit) or ry/by . the chip erase begins on the rising edge of the last ce or we , whichever happens first in the command sequence, and terminates when the data on dq 7 is 1 (see write operation status section), at which time the device returns to the read mode. chip erase time; sector erase time all sectors + chip program time (preprogramming) embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase command sector erase is a six bus cycle operation. there are two unlock write cycles. these are followed by writing the set-up command. two more unlock write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of ce or we , whichever happens later, while the command (data = 30h) is latched on the rising edge of ce or we , whichever happens first. after time-out of t tow from the rising edge of the last sector erase command, the sector erase operation begins. multiple sectors may be erased concurrently by writing the six bus cycle operations on mbm29qm12dh com- mand definitions table in n device bus operation. this sequence is followed by writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than t tow . otherwise, that command will not be accepted and erasure will not start. it is recommended that processor interrupts be disabled during this time to guarantee such a condition. the interrupts can reoccur after the last sector erase command is written. a time-out of t tow from the rising edge of last ce or we , whichever happens first, will initiate the execution of the sector erase command (s) . if another falling edge of ce or we , whichever happens first occurs within the t tow time-out window, the timer is reset (monitor dq 3 to determine if the sector erase timer window is still open, see section dq 3 , sector erase timer). resetting the device once execution has begun will corrupt the data in the sector. in that case, restart the erase on those sectors and allow them to complete (refer to write operation status section for sector erase timer operation). loading the sector erase buffer may be done in any sequence and with any number of sectors. sector erase does not require the user to program the device before erase. the device automatically programs all memory locations in the sector (s) to be erased prior to electrical erase (preprogram function) . when erasing a sector, the rest remain unaffected. the system is not required to provide any controls or timings during these operations. the system can determine the status of the erase operation by using dq 7 (data polling) , dq 6 (toggle bit) or ry/by . the sector erase begins after the t tow time-out from the rising edge of ce or we , whichever happens first, for the last sector erase command pulse and terminates when the data on dq 7 is 1 (see write operation status section), at which time the device returns to the read mode. data polling and toggle bit must be performed at an address within any of the sectors being erased. multiple sector erase time = [sector erase time + sector program time (preprogramming) ] number of sector erase in case of multiple sector erase across bank boundaries, a read from the bank (read-while-erase) to which sectors being erased belong cannot be performed. embedded erase tm algorithm in n flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations.
mbm29qm12dh -60 35 erase suspend/resume command the erase suspend command allows the user to interrupt sector erase operation and then reads data from or programs to a sector not being erased. this command is applicable only during the sector erase operation which includes the time-out period for sector erase. writing the erase suspend command (b0h) during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command (30h) resumes the erase operation. the bank address of sector being erased or erase-suspended should be set when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device takes a maximum of t spd to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin will be at high-z and the dq 7 bit will be at logic 1, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode, except that the data must be read from sectors that have not been erase-suspended. reading successively from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle (see the section on dq 2 ). after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for program. this program mode is known as the erase-suspend-program mode. again, it is the same as programming in the regular program mode, except that the data must be programmed to sectors that are not erase-suspended. reading successively from the erase-suspended sector while the device is in the erase-suspend-program mode will cause dq 2 to toggle. the end of the erase-suspended program operation is detected by the ry/by output pin, data polling of dq 7 or by the toggle bit i (dq 6 ), which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address within bank being erase-suspended. to resume the operation of sector erase, the resume command (30h) should be written to the bank being erase suspended. any further writes of the resume command at this point will be ignored. another erase suspend command can be written after the chip has resumed erasing. extended command (1) fast mode the device has a fast mode function. it dispenses with the initial two unclock cycles required in the standard program command sequence by writing the fast mode command into the command register. in this mode, the required bus cycle for programming consists of two bus cycles instead of four in standard program command. during the fast mode, do not write any commands other than the fast program/fast mode reset command. the read operation is also executed after exiting from the fast mode. to exit from this mode, it is necessary to write fast mode reset command into the command register. the first cycle must contain the bank address (see embedded program algorithm fot fast mode in n flow chart) .the v cc active current is required even if ce = v ih during fast mode. (2) fast programming during the fast mode, programming can be executed with two bus cycle operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd) (see embedded program algorithm fot fast mode in n flow chart) . (3) cfi (common flash memory interface) the cfi (common flash memory interface) specification outlines device and the host system software interro- gation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent and forward-and backward-compatible soft- ware support for the specified flash device families. refer to cfi specification in detail. the operation is initiated by writing the query command (98h) into the command register. the bank address should be set when writing this command. then the device information can be read from the bank, and data from the memory cell can be read from the another bank. the higher order address (a 22 , a 21 , a 20 ) required for reading out the cfi codes requires that the bank address (ba) be set at the write cycle. following the command write, a read cycle from specific address retrieves device information. please note that output data of upper byte (dq 15 to dq 8 ) is 0 . refer to cfi code table (common flash memory interface code table ) in n flexible
mbm29qm12dh -60 36 sector-erase architecture. to terminate operation, it is necessary to write the read/reset command sequence into the register. hiddenrom entry command the device has a hiddenrom area with one time protect function. this area is to enter the security code and to unable the change of the code once set. programming is allowed in this area until it is protected. however, once it gets protected, it is impossible to unprotect. therefore, extreme caution is required. the hiddenrom area is 128 words (64 words for factory and 64 words for customer). this area is normally the outermost 4 kwords boot block area. therefore, write the hiddenrom entry command sequence to enter the hiddenrom area. it is called hiddenrom mode when the hiddenrom area appears. sectors other than the boot block area (sa0) can be read during hiddenrom mode. read/program of the hiddenrom area is possible during hiddenrom mode. write the hiddenrom reset command sequence to exit the hiddenrom mode. the bank address of the hiddenrom should be set on the third cycle of this reset command sequence. in hiddenrom mode, the simultaneous operation cannot be executed multi-function mode between the hiddenrom area and the bank a. the following commands are unavailable when the hiddenrom is enabled. issuing the following commands while the hiddenrom is enabled results in the command being ignored. 1. cfi 2. set to fast mode 3. fast program 4. reset from fast mode 5. program and sector erase suspend 6. program and sector erase resume the hiddenrom entry command is allowed when the device is in either program or erase suspend modes. if the hiddenrom is enabled, the program or erase suspend command is ignored. this prevents resuming either programming or erasure on the hiddenrom if the overlayed sector was undergoing programming or erasure. it is the responsibility of the software to resume the program or erasure of a suspended program or erase after exiting the hiddenrom. hiddenrom program command to program the data to the hiddenrom area, write the hiddenrom program command sequence during hiddenrom mode. this command is the same as the program command in usual except to write the command during hiddenrom mode. therefore the detection of completion method is the same as in the past, using the dq 7 data polling, and dq 6 toggle bit. need to pay attention to the address to be programmed. if the address other than the hiddenrom area is selected to program, data of the address will be changed. hiddenrom protect command the method to protect the hiddenrom is to apply high voltage (v id ) to a 9 and oe , set the sector address in the hiddenrom area and (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 1, 0, 1, 0), and apply the write pulse during the hiddenrom mode. to verify the protect circuit, apply high voltage (v id ) to a 9 , specify (a 7 , a 6 , a 5 , a 4 , a 3 , a 2 , a 1 , a 0 ) = (0, 0, 0, 1, 1, 0, 1, 0) and the sector address in the hiddenrom area, and read. when 1 appears on dq 0 , the protect setting is completed. 0 will appear on dq 0 if it is not protected. please apply write pulse agian. and the device has also hiddenrom protect command wirhout v id . see mbm29qm12dh command definitions ta b l e i n n device bus operation. other sector will be effected if the address other than those for hiddenrom area is selected for the sector address, so please be carefull. once it is protected, protection can not be cancelled, so please pay the closest attention.
mbm29qm12dh -60 37 password program command the password program command permits programming the password that is used as part of the hardware protection scheme. the actual password is 64-bits long. 4 password program commands are required to program the password. the user must enter the unlock cycle, password program command (38h) and the program address/data for each portion of the password when programming. there are no provisions for entering the 2- cycle unlock cycle, the password program command, and all the password data. there is no special addressing order required for programming the password. also, when the password is undergoing programming, simulta- neous operation is disabled. read operations to any memory location will return the programming status. once the password is written and verified, the password mode locking bit must be set in order to prevent verification. the password program command is only capable of programming 0s. programming a 1 after a cell is programmed as a 0 results in a time-out by the embedded program algorithm with the cell remaining as a 0. the password is all fs when shipped from the factory. all 64-bit password combinations are valid as a password. writing the hiddenrom exit command returns the device back to normal operation. password verify command the password verify command is used to verify the password. the password is verifiable only when the password mode locking bit is not programmed. if the password mode locking bit is programmed and the user attempts to verify the password, the device will always drive all fs onto the dq data bus. also, the device will not operate in simultaneous operation when the password verify command is executed. only the password is returned regardless of the bank address. the lower two address bits (a 1 :a 0 ) are valid during the password verify. writing the hiddenrom exit command returns the device back to normal operation. password protection mode locking bit program command the password protection mode locking bit program command programs the password protection mode locking bit, which prevents further verifies or updates to the password. once programmed, the password protection mode locking bit cannot be erased. once the password protection mode locking bit is programmed, the presistent sector protection locking bit program circuitry is disabled, thereby forcing the device to remain in the password protection mode. after issuing "pl/68h" at 4th bus cycle, the device requires approximately 150 s time out period for programming the password protection mode locking bit. then by writing "pl/48h" at 5th bus cycle, the device outputs verify data at dq 0 . if dq 0 = 1 then password protection mode locking bit is programmed. if not, then the user needs to repeat this program sequence from the 4th cycle of "pl/68h". exiting the password protection mode locking bit program command is accomplished by writing the hiddenrom exit command. persistent sector protection mode locking bit program command the persistent sector protection mode locking bit program command programs the persistent sector protection mode locking bit, which prevents the password mode locking bit from ever being programmed. by disabling the program circuitry of the password mode locking bit, the device is forced to remain in the persistent sector protection mode of operation, once this bit is set. after issuing "spml/68h" at 4th bus cycle, the device requires approximately 150 s time out period for programming the persistent protection mode locking bit. then by writing "spml/48h" at 5th bus cycle, the device outputs verify data at dq 0 . if dq 0 = 1 then persistent protection mode locking bit is programmed. if not, then the user needs to repeat this program sequence from the 4th cycle of "spml/68h". exiting the persistent protection mode locking bit program command is accomplished by writing the hiddenrom exit command. ppb lock bit set command the ppb lock bit set command is used to set the ppb lock bit if it is cleared either at reset or if the password unlock command was successfully executed. there is no ppb lock bit clear command. once the ppb lock bit is set, it cannot be cleared unless the device is taken through a power-on clear or the password unlock command is executed. if the password mode locking bit is set, the ppb lock bit status is reflected as set, even after a power-on reset cycle. exiting the ppb lock bit set command is accomplished by writing the hiddenrom exit command.
mbm29qm12dh -60 38 dpb write(erase) command the dpb write command is used to set or clear a dpb for a given sector. the high order address bits (a 22 to a 12 ) are issued at the same time as the code 01h or 00h on dq 7 to dq 0 . all other dq data bus pins are ignored during the data write cycle. the dpbs are modifiable at any time, regardless of the state of the ppb or ppb lock bit. the dpbs are cleared at power-up or hardware reset.exiting the dpb write command is accomplished by writing the hiddenrom exit command. dpb verify command dpb verify command is uesed to verify the status of a dpb for given sector.scanning the sector addresses (sa) will produce a logical "1" at the device output dq 0 for a protected sector. otherwise the device will produce "0" at dq 0 for the sector which is not protected. writing the hiddenrom exit command returns the device back to normal operation. ppb lock bit verify command ppb lock bit verify command is used to verify the status of a ppb lock bit. a logical "1" at the device output dq 1 indicates that the ppb lock bit is set. if ppb lock bit is not set, dq 1 will output "0". writing the hiddenrom exit command returns the device back to normal operation. password unlock command the password unlock command is used to clear the ppb lock bit so that the ppbs can be unlocked for modification, thereby allowing the ppbs to become accessible for modification. the exact password must be entered in order for the unlocking function to occur. this command cannot be issued any faster than 2 m s at a time to prevent a hacker from running through the all 64-bit combinations in an attempt to correctly match a password. if the command is issued before the 2 m s execution window for each portion of the unlock, the command will be ignored. the password unlock function is accomplished by writing password unlock command and data to the device to perform the clearing of the ppb lock bit. a 0 and a 1 are used to determine the 16 bit data quantity is used to match separated 16 bits. writing the password unlock command is address order specific. in other words, the lowers address a 1 :a 0 = 00, the next cycle command is to a 1 :a 0 = 01, then to a 1 :a 0 = 10, and finally to a 1 :a 0 = 11. writing out of sequence results in the password unlock not returning a match with the password and the ppb lock bit remains set. once the password unlock command is entered, the ry/by pin goes low indicating that the device is busy. also, reading the bank a results in the dq 6 pin toggling, indicating that the password unlock function is in progress. reading the other bank returns actual array data. approximately 2 s is required for each portion of the unlock. once the first portion of the password unlock completes (ry/by is not driven and dq 6 does not toggle when read), the next cycle is issued, only this time with the next part of the password. seven cycles password unlock commands are required to successfully clear the ppb lock bit. as with the first password unlock command, the ry/by signal goes low and reading the device results in the dq 6 pin toggling on successive read operations until complete. it is the responsibility of the microprocessor to keep track of the number of password unlock cycles, the order, and when to read the ppb lock bit to confirm successful password unlock. writing the hiddenrom exit command returns the device back to normal operation. ppb program command the ppb program command is used to program, or set, a given ppb. each ppb is individually programmed (but is bulk erased with the other ppbs). the specific sector address (a 22 to a 12 ) are written at the same time as the program command 60h. if the ppb lock bit is set and the corresponding ppb is set for the sector, the ppb program command will not execute and the command will time-out without programming the ppb. after issuing "sga + wp/68h" at 4th bus cycle, the device requires approximately 150 s time out period for program- ming the ppb. then by writing "sga + wp/48h" at 5th bus cycle, the device outputs verify data at dq 0 . if dq 0 = 1 then ppb is programmed. if not, then the user needs to repeat this program sequence from the 4th cycle of "sga + wp/68h". the ppb program command does not follow the embedded program algorithm. writing the hiddenrom exit command returns the device back to normal operation.
mbm29qm12dh -60 39 all ppb erase command the all ppb erase command is used to erase all ppbs in bulk. there is no means for individually erasing a specific ppb. unlike the ppb program, no specific sector address is required. however, when the ppb erase command is written (60h), all sector ppbs are erased in parallel. if the ppb lock bit is set the all ppb erase command will not execute and the command will time-out without erasing the ppbs. after issuing "wp/60h" at 4th bus cycle, the device requires approximately 1.5 ms time out period for programming the ppb. then by writing "sga + wp/40h" at 5th bus cycle, the device outputs verify data at dq 0 . if dq 0 = 0 then ppb is successfully erased. if not, then the user needs to repeat this program sequence from the 4th cycle of "wp/60h". it is the responsibility of the user to preprogram all ppbs prior to issuing the all ppb erase command. if the user attempts to erase a cleared ppb, over-erasure may occur making it difficult to program the ppb at a later time. also note that the total number of ppb program/erase cycles is limited to 100 cycles. cycling the ppbs beyond 100 cycles is not guaranteed. writing the hiddenrom exit command returns the device back to normal operation. write operation status detailed in hardware sequence flags table in n command definition are all the status flags which can determine the status of the bank for the current mode operation. the read operation from the bank which doesnt operate embedded algorithm returns data of memory cells. these bits offer a method for determining whether an embedded algorithm is properly completed. the information on dq 2 is address-sensitive. this means that if an address from an erasing sector is consecutively read, the dq 2 bit will toggle. however, dq 2 will not toggle if an address from a non-erasing sector is consecutively read. this allows users to determine which sectors are in erase and which are not. the status flag is not output from banks (non-busy banks) which do not execute embedded algorithms. for example, a bank (busy bank) is executing an embedded algorithm. when the read sequence is [1] < busy bank >, [2] < non-busy bank >, [3] < busy bank >, the dq 6 toggles in the case of [1] and [3]. in case of [2], the data of memory cells are output. in the erase-suspend read mode with the same read sequence, dq 6 will not be toggled in [1] and [3]. in the erase suspend read mode, dq 2 is toggled in [1] and [3]. in case of [2], the data of memory cell is output. hardware sequence flags table *1 : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. *2 : reading from non-erase suspend sector address will indicate logic 1 at the dq 2 bit. status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle* 1 program suspended mode program suspend read (program suspended sector) data data data data data program suspend read (non-program suspended sector) data data data data data erase suspended mode erase suspend read (erase suspended sector) 1 1 0 0 toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle 0 0 1* 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
mbm29qm12dh -60 40 dq 7 data polling the device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the device will produce a complement of data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device will produce true data last written to dq 7 . for programming, the data polling is valid after the rising edge of the fourth write pulse in the four write pulse sequences. during the embedded erase algorithm, an attempt to read the device will produce a 0 at the dq 7 output. upon completion of the embedded erase algorithm, an attempt to read device will produce a 1 on dq 7 . the flowchart for data polling (dq 7 ) is shown in temporary sector group unprotection algorithm in n flow chart. data polling will also flag the entry into erase suspend. dq 7 will switch 0 to 1 at the start of the erase suspend mode. please note that the address of an erasing sector must be applied in order to observe dq 7 in the erase suspend mode. for chip erase and sector erase, the data polling is valid after the rising edge of the sixth write pulse in the six write pulse sequences. data polling must be performed at sector addresses of sectors being erased, not pro- tected sectors. otherwise the status may become invalid. if a program address falls within a protected sector, data polling on dq 7 is active for approximately 1 m s, then that bank returns to the read mode. after an erase command sequence is written, if all sectors selected for erasing are protected, data polling on dq 7 is active for approximately 400 m s, then the bank returns to read mode. once the embedded algorithm operation is close to being completed, the device data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that device is driving status information on dq 7 at one instant, and then that bytes valid data at the next instant. depending on when the system samples the dq 7 output, it may read the status or valid data. even if device has completed the embedded algorithm operation and dq 7 has a valid data, data outputs on dq 0 to dq 6 may still be invalid. the valid data on dq 0 to dq 7 will be read on successive read attempts. the data polling feature is active only during the embedded programming algorithm, embedded erase algorithm or sector erase time-out. (see hardware sequence flags table in n command definition.) see data polling during embedded algorithm operation timing diagram in n timing diagram for the data polling timing specifications and diagrams. dq 6 toggle bit i the device also features the toggle bit i as a method to indicate to the host system that the embedded algorithms are in progress or completed. during embedded program or erase algorithm cycle, successive attempts to read (oe toggling) data from the busy bank will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data will be read on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth write pulse in the four write pulse sequences. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth write pulse in the six write pulse sequences. the toggle bit i is active during the sector time out. in programming, if the sector being written is protected, the toggle bit will toggle for about 1 m s and then stop toggling with data unchanged. in erase, the device will erase all selected sectors except for protected ones. if all selected sectors are protected, the chip will toggle the toggle bit for about 400 s and then drop back into read mode, having data kept remained. either ce or oe toggling will cause dq 6 to toggle. in addition, an erase suspend/resume command will cause dq 6 to toggle. the system can use dq 6 to determine whether a sector is actively erased or is erase-suspended. when a bank is actively erased (that is, the embedded erase algorithm is in progress) , dq 6 toggles. when a bank enters the erase suspend mode, dq 6 stops toggling. successive read cycles during erase-suspend-program cause dq 6 to toggle.
mbm29qm12dh -60 41 to operate toggle bit function properly, ce or oe must be high when bank address is changed. see data polling during embedded algorithm operation timing diagram in n timing diagram for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count) . under these conditions dq 5 will produce 1. this is a failure condition indicating that the program or erase cycle was not successfully completed. data polling is only operating function of the device under this condition. the ce circuit will partially power down device under these conditions (to approximately 2 ma) . the oe and we pins will control the output disable functions as described in mbm29qm12dh user bus operations table in n device bus operation. the dq 5 failure condition may also appear if a user tries to program a non-blank location without pre-erase. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads valid data on dq 7 bit and dq 6 never stop toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a 1. please note that this is not a device failure condition since the device was incorrectly used. if this occurs, reset device with the command sequence. dq 3 sector erase timer after completion of the initial sector erase command sequence, sector erase time-out begins. dq 3 will remain low until the time-out is completed. data polling and toggle bit are valid after the initial sector erase command sequence. if data polling or the toggle bit i indicates that a valid erase command has been written, dq 3 may be used to determine whether the sector erase timer window is still open. if dq 3 is high (1) the internally controlled erase cycle has begun. if dq 3 is low (0) , the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 were high on the second status check, the command may not have been accepted. see hardware sequence flags table in n command definition : hardware sequence flags. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the non-erase suspended sector will indicate a logic 1 at the dq 2 bit. dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. the behavior of these two status bits, along with that of dq 7 , is summarized as follows : for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also toggle bit status table in n command definition and dq 2 vs. dq 6 in n timing diagram. furthermore dq 2 can also be used to determine which sector is being erased. at the erase mode, dq 2 toggles if this bit is read from an erasing sector. to operate toggle bit function properly, ce or oe must be high when bank address is changed.
mbm29qm12dh -60 42 reading toggle bits 3dq 6 /dq 2 whenever the system initially begins reading toggle bit status, it must read dq 7 to dq 0 at least twice in a row to determine whether a toggle bit is toggling. typically a system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7 to dq 0 on the following read cycle. however, if, after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq 5 is high (see the section on dq 5 ) . if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq 5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq 5 has not gone high. the system may continue to monitor the toggle bit and dq 5 through successive read cycles, deter- mining the status as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. (refer to toggle bit algorithm in n flow chart.) toggle bit status table * : successive reads from the erasing or erase-suspend sector will cause dq 2 to toggle. reading from the non erase suspend sector address will indicate logic 1 at the dq 2 bit. ry/by ready/busy the device provides a ry/by open-drain output pin as a way to indicate to the host system that embedded algorithms are either in progress or have been completed. if output is low, the device is busy with either a program or erase operation. if output is high, the device is ready to accept any read/write or erase operation. if the device is placed in an erase suspend mode, ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth write pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth write pulse. the ry/by pin will indicate a busy condition during reset pulse. refer to ry/by timing diagram during program/erase operation timing diagram in n timing diagram and reset , ry/by timing diagram in n timing diagram for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, ry/by pins can be tied together in parallel with a pull-up resistor to v cc . data protection the device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power-up, the device automatically resets the internal state machine in read mode. also, with its control register architecture, alteration of memory contents only occurs after successful completion of specific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from v cc power-up and power-down transitions or system noise. mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle* erase-suspend read (erase-suspended sector) 11toggle erase-suspend program dq 7 toggle 1*
mbm29qm12dh -60 43 low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than v lko (min) . if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until the v cc level is greater than v lko . it is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when v cc is above v lko (min) . if the embedded erase algorithm is interrupted, the intervened erasing sector (s) is (are) not valid. write pulse glitch protection noise pulses of less than 3 ns (typical) on oe , ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih or we = v ih . to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the device with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to the read mode on power-up.
mbm29qm12dh -60 44 n absolute maximum ratings *1 : voltage is defined on the basis of v ss = gnd = 0 v. *2 : minimum dc voltage on input or i/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc voltage on input or i/o pins is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods of up to 20 ns. *3 : minimum dc input voltage on a 9 , oe and reset pins is - 0.5 v. during voltage transitions, a 9 , oe and reset pins may undershoot v ss to - 2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in - v cc ) does not exceed + 9.0 v. maximum dc input voltage on a 9 , oe and reset pins is + 13.0 v which may overshoot to + 14.0 v for periods of up to 20 ns. *4 : minimum dc input voltage on wp /acc pin is - 0.5 v. during voltage transitions, wp /acc pin may undershoot v ss to - 2.0 v for periods of up to 20 ns. maximum dc input voltage on wp /acc pin is + 10.5 v which may overshoot to + 12.0 v for periods of up to 20 ns when vcc is applied. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. n recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0 v. note : operating ranges define those limits between which the proper device function is guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating conditionranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg - 55 + 125 c ambient temperature with power applied t a - 40 + 85 c voltage with respect to ground all pins except a 9 , oe , and reset * 1, * 2 v in , v out - 0.5 v cc + 0.5 v power supply voltage * 1 v cc - 0.5 + 4.0 v a 9 , oe , and reset * 1, * 3 v in - 0.5 + 13.0 v wp /acc * 1, * 4 v acc - 0.5 + 10.5 v parameter symbol part no. value unit min max ambient temperature t a mbm29qm12dh 60/70 - 40 + 85 c power supply voltage v cc mbm29qm12dh 60/70 + 2.7 + 3.6 v v ccq supply voltage* v ccq mbm29qm12dh 60 + 2.7 + v cc v mbm29qm12dh 70 + 1.65 + 1.95 v
mbm29qm12dh -60 45 n maximum overshoot/maximum undershoot maximum undershoot waveform + 0.8 v C0.5 v 20 ns C2.0 v 20 ns 20 ns maximum overshoot waveform 1 + 2.0 v v cc + 0.5 v 20 ns v cc + 2.0 v 20 ns 20 ns maximum overshoot waveform 2 v cc + 0.5 v + 13.0 v 20 ns + 14.0 v 20 ns 20 ns note: this waveform is applicable for a 9 , oe , and reset .
mbm29qm12dh -60 46 n dc characteristics 1. dc characteristics (v ccq = = = = 2.7 v to 3.6 v or 1.65 v to 1.95 v) *1: the i cc current listed includes both the dc operating current and the frequency dependent component. *2: i cc active while embedded algorithm (program or erase) is in progress. *3: automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4: applicable for only v cc . *5: embedded algorithm (program or erase) is in progress. (@5 mhz) parameter sym bol conditions value un it min typ max input leakage current i li v in = v ssq to v ccq , v cc = v cc max - 1.0 ?+ 1.0 a output leakage current i lo v out = v ssq to v ccq , v cc = v cc max - 1.0 ?+ 1.0 a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v ??+ 35 a wp /acc accelerated program current i lia v cc = v cc max, wp /acc = v acc max ?? 20 ma v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 10 mhz v cc = 2.7 v to 3.1 v ?? 45 ma v cc = 2.7 v to 3.6 v ?? 60 ce = v il , oe = v ih , f = 5 mhz v cc = 2.7 v to 3.1 v ?? 25 ma v cc = 2.7 v to 3.6 v ?? 30 v cc active current * 2 i cc2 ce = v il , oe = v ih ?? 25 ma v cc current (standby) i cc3 v cc = v cc max, ce = v ccq 0.3 v, reset = v ccq 0.3 v,wp /acc = v ccq 0.3 v ? 15a v cc current (standby, reset) i cc4 v cc = v cc max, reset = v ssq 0.3 v ? 15a v cc power supply current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ssq 0.3 v, reset = v ccq 0.3 v, v in = v ccq 0.3 v or v ssq 0.3 v ? 15a v cc active current * 5 (read-while-program) i cc6 ce = v il , oe = v ih ?? 45 ma v cc active current * 5 (read-while-erase) i cc7 ce = v il , oe = v ih ?? 45 ma v cc active current (erase-suspend-program) i cc8 ce = v il , oe = v ih ?? 25 ma v cc active current (page mode read) i cc9 ce = v il , oe = v ih , 8 words read v cc = 2.7 v to 3.1 v ?? 10 ma v cc = 2.7 v to 3.6 v ?? 15 input low level v il ?- 0.5 ? v ccq 0.3 v input high level v ih ? 0.7 v ccq ? v ccq + 0.3 v voltage for autoselect and sector protection (a 9 , oe , reset ) * 4 v id ? 11.5 12 12.5 v voltage for wp /acc sector protection/unprotection and program acceleration * 4 v acc ? 8.5 9.0 9.5 v output low voltage level v ol i ol = 100 a, v cc = v cc min ?? 0.15 v ccq v output high voltage level v oh2 i oh = - 100 a 0.85 v ccq ?? v low v cc lock-out voltage v lko ? 2.3 2.4 2.5 v
mbm29qm12dh -60 47 n ac characteristics ? read only operations characteristics parameter symbol test setup value unit v ccq = = = = 2.7 v to 3.6 v * 1 v ccq = = = = 1.65 v to 1.95 v * 2 jedec standard min max min max read cycle time t avav t rc ? 60 ? 70 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 60 ? 70 ns page read cycle time ? t prc ? 20 ? 30 ? ns page address to output delay ? t pacc ce = v il oe = v il ? 20 ? 30 ns chip enable to output delay t elqv t ce oe = v il ? 60 ? 70 ns output enable to output delay t glqv t oe ?? 20 ? 30 ns chip enable to output high-z t ehqz t df ?? 20 ? 30 ns output enable to output high-z t ghqz t df ?? 20 ? 30 ns output hold time from address, ce or oe , whichever occurs first t axqx t oh ? 5 ? 5 ? ns *1 : test conditions: output load: 1 ttl gate and 30 pf (figure 4.1) input rise and fall times: 5 ns input pulse levels: 0.0 v or v ccq timing measurement reference level input: 0.5 v ccq output:0.5 v ccq *2 : test conditions: output load: c l = 30 pf (figure 4.2) input rise and fall times: 5 ns input pulse levels: 0.0 v or v ccq timing measurement reference level input: 0.5 v ccq output:0.5 v ccq c l device under test figure 4.2 test conditions c l 3.3 v diode = 1n3064 or equivalent 2.7 k w device under test diode = 1n3064 or equivalent 6.2 k w figure 4.1 test conditions
mbm29qm12dh -60 48 ? write (erase/program) operations (continued) parameter symbol value unit v ccq = = = = 2.7 v to 3.6 v * 1 v ccq = = = = 1.65 v to 1.95 v * 2 jedec standard min typ max min typ max write cycle time t avav t wc 60 ?? 70 ?? ns address setup time t avwl t as 0 ?? 0 ?? ns address setup time to oe low during toggle bit polling ? t aso 15 ?? 15 ?? ns address hold time t wlax t ah 30 ?? 35 ?? ns address hold time from ce or oe high during toggle bit polling ? t aht 0 ?? 0 ?? ns data setup time t dvwh t ds 25 ?? 30 ?? ns data hold time t whdx t dh 0 ?? 0 ?? ns output enable setup time ? t oes 0 ?? 0 ?? ns output enable hold time read ? t oeh 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? ns read recover time before write (oe high to ce low) t ghel t ghel 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? ns write pulse width t wlwh t wp 35 ?? 40 ?? ns ce pulse width t eleh t cp 35 ?? 40 ?? ns write pulse width high t whwl t wph 20 ?? 25 ?? ns ce pulse width high t ehel t cph 20 ?? 25 ?? ns word programming operation t whwh1 t whwh1 ? 6 ?? 6 ? s sector erase operation* 1 t whwh2 t whwh2 ? 0.5 ?? 0.5 ? s v cc setup time ? t vcs 50 ?? 50 ?? s rise time to v id * 2 ? t vidr 500 ?? 500 ?? ns rise time to v acc * 3 ? t vaccr 500 ?? 500 ?? ns voltage transition time* 2 ? t vlht 4 ?? 4 ?? s write pulse width* 2 ? t wpp 100 ?? 100 ?? s oe setup time to we active* 2 ? t oesp 4 ?? 4 ?? s ce setup time to we active* 2 ? t csp 4 ?? 4 ?? s
mbm29qm12dh -60 49 (continued) *1: this does not include the preprogramming time. *2: this timing is for sector protection operation. *3: this timing is for accelerated program operation. parameter symbol value unit v ccq = = = = 2.7 v to 3.6 v * 1 v ccq = = = = 1.65 v to 1.95 v * 2 jedec standard min typ max min typ max recover time from ry/by t rb 0 0 ns reset pulse width t rp 500 500 ns reset high level period before read t rh 50 50 ns program/erase valid to ry/by delay t busy 90 90 ns delay time from embedded output enable t eoe 60 70 ns sector erase time-out period t tow 50 50 s erase suspend transition time t spd 20 20 s
mbm29qm12dh -60 50 n erase and programming performance note : typical erase conditions t a = + 25c, v cc = 2.9 v typical program conditions t a = + 25c, v cc = 2.9 v, data = checker n tsop(1) pin capacitance (t a = + 25c, f = 1.0 mhz) n fbga pin capacitance parameter limits unit comments min typ max sector erase time ? 0.5 2 s excludes programming time prior to erasure word programming time ? 6.0 100 s excludes system-level overhead chip programming time ? 50.3 200 s excludes system-level overhead erase/program cycle 100,000 ?? cycle ? parameter symbol test setup value unit typ max input pin capacitance c in v in = 0710pf output pin capacitance c out v out = 0812pf control pin capacitance c in2 v in = 0811pf control pin capacitance (wp /acc) c in3 v in = 01112pf parameter symbol test setup value unit typ max input pin capacitance c in v in = 0 7 10 pf output pin capacitance c out v out = 0 8 12 pf control pin capacitance c in2 v in = 0 8 11 pf control pin capacitance (wp /acc) c in3 v in = 01112pf
mbm29qm12dh -60 51 n timing diagram ? key to switching waveforms read operation timing diagram waveform inputs outputs must be steady may change from h to l may change from l to h "h" or "l": any change permitted does not apply will be steady will change from h to l will change from l to h changing, state unknown center line is high- impedance "off" state address address stable high-z high-z ce oe we outputs outputs valid t rc t acc t oe t df t ce t oh t oeh
mbm29qm12dh -60 52 same page address we oe ce a 22 to a 3 a 2 to a 0 output t rc t ce t acc aa ab ac ad ae af ag ah t prc t prc t oe t oeh t pacc t pacc t pacc high-z t oh t oh t oh t oh t oh t oh t oh t oh da db dc dh t df t prc t prc t prc t prc t prc t pacc t pacc t pacc dd de df t pacc dg page read operation timing diagram address ce reset outputs high-z outputs valid address stable t rc t acc t rh t rp t rh t ce t oh hardware reset/read operation timing diagram
mbm29qm12dh -60 53 alternate we controlled program operation timing diagram address data ce oe we 3rd bus cycle data polling 555h pa a0h pd dq 7 d out d out pa t wc t as t ah t rc t ce t whwh1 t wph t wp t ghwl t ds t dh t df t oh t oe t cs t ch notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence.
mbm29qm12dh -60 54 alternate ce controlled program operation timing diagram address data we oe ce 3rd bus cycle data polling 555h pa a0h pd dq 7 d out pa t wc t as t ah t whwh1 t cph t cp t ghel t ds t dh t ws t wh notes : pa is address of the memory location to be programmed. pd is data to be programmed at word address. dq 7 is the output of the complement of the data written to the device. d out is the output of the data written to the device. figure indicates last two bus cycles out of four bus cycle sequence.
mbm29qm12dh -60 55 address data v cc ce oe we 555h 2aah 555h 555h 2aah sa* t wc t as t ah t cs t ghwl t ch t wp t ds t vcs t dh t wph aah 55h 80h aah 55h 10h/ 30h 10h for chip erase chip/sector erase operation timing diagram * : sa is the sector address for sector erase. addresses = 555h (at word mode) for chip erase.
mbm29qm12dh -60 56 data polling during embedded algorithm operation timing diagram t oeh t ch t oe t ce t df t busy t eoe t whwh1 or 2 ce dq 7 dq 6 to dq 0 ry/by dq 7 dq 7 = valid data dq 6 to dq 0 = output flag dq 6 to dq 0 valid data oe we high-z high-z data data * * : dq 7 = valid data (the device has completed the embedded operation) .
mbm29qm12dh -60 57 t dh t oe t ce ce we oe dq 6 /dq 2 address ry/by data toggle data toggle data toggle data stop toggling output valid * t busy t oeh t oeh t oeph t aht t aht t aso t as t ceph ac waveforms for toggle bit i during embedded algorithm operations * : dq 6 stops toggling (the device has completed the embedded operation). note : dq 6 : addresses are "bank address" where embedded algorithm is in progress. dq 2 : addresses are "sector address" where embedded algorithm (erase) is in progress.
mbm29qm12dh -60 58 ce dq we address ba1 ba1 ba1 ba2 (555h) ba2 (pa) ba2 (pa) oe valid output valid output valid output status valid intput valid intput t rc t rc t rc t rc t wc t wc t aht t as t as t ah t acc t ce t oe t oeh t wp t ghwl t ds t df t dh t df t ceph read command command read read read (a0h) (pd) bank-to-bank read/write timing diagram note : this is example of read for bank 1 and embedded algorithm (program) for bank 2. ba1 : address corresponding to bank 1 ba2 : address corresponding to bank 2 enter embedded erasing erase suspend erase resume enter erase suspend program erase suspend program erase complete erase erase suspend read erase suspend read erase dq 6 dq 2 * we toggle dq 2 and dq 6 with oe or ce dq 2 vs. dq 6 * : dq 2 is read from the erase-suspended sector.
mbm29qm12dh -60 59 ce ry/by we rising edge of the last we signal t busy entire programming or erase operations ry/by timing diagram during program/erase operation timing diagram t rp t rb t ready ry/by we reset reset , ry/by timing diagram
mbm29qm12dh -60 60 t wpp t vlht t vlht t oe t csp t oesp t vcs t vlht t vlht a 22 , a 21 , a 20 a 19 , a 18 , a 17 a 16 , a 15 , a 14 a 13 , a 11 a 7 , a 6 , a 5 a 4 , a 3 , a 2 a 0 a 1 a 9 v cc oe v id v ih v id v ih we ce data sgax 01h sgay sector group protection timing diagram sgax : sector group address to be protected sgay : next sector group address to be protected
mbm29qm12dh -60 61 unprotection period t vlht t vlht t vcs t vlht t vidr program or erase command sequence v cc v id v ih we ry/by ce reset temporary sector group unprotection timing diagram
mbm29qm12dh -60 62 v cc we oe ce reset t wc t wc t vlht t vidr t vcs time-out sgax sgax sgay t wp t oe 60h 01h 40h 60h 60h data address a 7 , a 6 , a 5 a 4 , a 3 , a 2 a 0 a 1 sgax : sector group address to be protected sgay : next sector group address time-out : time-out window = 250 m s (min) extended sector group protection timing diagram
mbm29qm12dh -60 63 v ih wp/acc vcc ce we ry/by t vlht program command sequence t vlht t vcs t vaccr vacc t vlht acceleration period accelerated program timing diagram
mbm29qm12dh -60 64 n flow chart embedded algorithm tm 555h/aah 555h/a0h 2aah/55h program address/program data programming completed last address ? increment address verify data ? data polling program command sequence (address/command) : write program command sequence (see below) start no no yes yes embedded program algorithm in program embedded program tm algorithm
mbm29qm12dh -60 65 embedded algorithm tm 555h/aah 555h/80h 2aah/55h 555h/aah 555h/10h 2aah/55h 555h/aah 555h/80h 2aah/55h 555h/aah sector address /30h sector address /30h sector address /30h 2aah/55h erasure completed data = ffh ? data polling write erase command sequence (see below) start no yes embedded erase algorithm in progress chip erase command sequence (address/command) : individual sector/multiple sector erase command sequence (address/command) : additional sector erase commands are optional. embedded erase tm algorithm
mbm29qm12dh -60 66 dq 7 = data? dq 5 = 1? fail pass dq 7 = data? * read (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va start no no no yes yes yes va = address for programming = any of the sector addresses within the sector being erased during sector erase or multiple erases operation. = any of the sector addresses within the sector not being protected during sector erase or multiple sector erases operation. data polling algorithm * : dq 7 is rechecked even if dq 5 = 1 because dq 7 may change simultaneously with dq 5 .
mbm29qm12dh -60 67 dq 6 = toggle? dq 5 = 1? read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va read dq 7 to dq 0 addr. = va start no no yes yes *1 *1, 2 dq 6 = toggle? no yes program/erase operation not complete.write reset command program/erase operation complete read dq 7 to dq 0 addr. = va *1 va = bank address being executed embedded algorithm. toggle bit algorithm *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to 1.
mbm29qm12dh -60 68 555h/aah 555h/20h xxxh/90h xxxh/f0h xxxh/a0h 2aah/55h program address/program data programming completed last address? increment address verify data? data polling start no no yes yes set fast mode in fast program reset fast mode (ba) embedded programming algorithm for fast mode
mbm29qm12dh -60 69 setup sector group addr. (a 22 , a 21 , a 20 , a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , a 12 ) activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes yes no no oe = v id , a 9 = v id , ce = v il , reset = v ih a 7 = a 6 = a 5 = a 4 = a 3 = a 2 = a 0 = v il , a 1 = v ih plscnt = 1 time out 100 m s remove v id from a 9 write reset command increment plscnt no yes protect another sector group? data = 01h? plscnt = 25? device failed remove v id from a 9 write reset command start sector group protection completed read from sector (addr. = sga, a 7 = a 6 = a 5 = a 4 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) sector group protection algorithm
mbm29qm12dh -60 70 start perform erase or program operations reset = v id *1 reset = v ih temporary sector group unprotection completed *2 temporary sector group unprotection algorithm *1 : all protected sector groups are unprotected. *2 : all previously protected sector groups are reprotected.
mbm29qm12dh -60 71 start no yes yes data = 01h? plscnt = 1 no no yes device failed plscnt = 25? remove v id from reset write reset command sector group protection completed protect other sector group? increment plscnt read from sector group address (addr. = sga, a 7 = a 6 = a 5 = a 4 = a 3 = a 2 = a 0 = v il , a 1 = v ih ) remove v id from reset write reset command time out 250 m s reset = v id wait 4 m s no yes setup next sector group address device is operating in temporary sector group unprotection mode to protect sector group write 60h to sector address a 7 = a 6 = a 5 = a 4 = a 3 = a 2 = a 0 = v il , a 1 = v ih to verify sector group protection write 40h to sector address a 7 = a 6 = a 5 = a 4 = a 3 = a 2 = a 0 = v il , a 1 = v ih to setup sector group protection write xxxh/60h first write cycle = 60h? () ( ) extended sector group protection algorithm
mbm29qm12dh -60 72 password sector protect algorithm password program dq 0 = 0? start password mode choice method reset command password protection dq 0 = 1? no (time out) mode bit program reset command password verify reset command sector protection yes yes no completed
mbm29qm12dh -60 73 ppb lock bit clear in password mode password unlock ry/by = h? start ppb lock clear in password mode dq 0 = 1? no (time out) reset command ppb lock bit yes password unlock dpb/ppb/ppb lock bit status no password/unlock complete reset command all ppb erase dq 0 = 0? yes no (time out) yes clear completed
mbm29qm12dh -60 74 n ordering information part no. package access time (ns) remarks mbm29qm12dh60pcn 56-pin plastic tsop (1) (fpt-56p-m01) normal bend 60 mbm29qm12dh60pbt 80-pin plastic fbga (bga-80p-m04) 60 mbm29qm12d h 60 pcn device number/description mbm29qm12d 128 mbit (8m 16-bit) page mode flash memory 3.0 v-only, page mode and dual operation flash memory package type pcn = 56-pin thin small outline package (tsop (1) normal bend) pbt = 80-pin fine pitch ball grid array package (fbga) speed option see product selector guide device revision
mbm29qm12dh -60 75 n package dimensions (continued) 56-pin plastic tsop(1) (fpt-56p-m01) note 1) *1 : resin protrusion. (each side : + 0.15 (.006) max) . note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width and pins thickness include plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm (inches) . note : the values in parentheses are reference values. c 2002 fujitsu limited f56001s-c-4-5 18.400.10(.724.004) 20.000.20(.787.008) 14.000.10 m 0.10(.004) 0.100.05 (.004.002) 1 28 56 29 0.08(.003) (.551.004) (stand off) lead no. details of "a" part 0.600.15 (.024.006) 0?~8? .007.001 0.170.03 0.220.05 (.009.002) (mounting height) index "a" .043 C.002 +.004 C0.05 +0.10 1.10 0.50(.020) 0.25(.010) * 1 * 2
mbm29qm12dh -60 76 (continued) 80-pin plastic fbga (bga-80p-m04) dimensions in mm (inches) . note : the values in parentheses are reference values. c 2003 fujitsu limited b80004s-c-1-1 11.000.10(.433.004) 8.000.10 (.315.004) 0.10(.004) 0.380.10 (.015.004) (stand off) .043 C.005 +.005 C0.13 +0.12 1.08 (mounting height) a b c d e f g h j k 8 7 6 5 4 3 2 1 (index area) 80-?0.450.05 (80-?.018.002) ml b a s m 0.08(.003) ref 0.80(.031) b ref 0.40(.016) a s (index area) s
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